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 17th October 2005, 09:49 #1
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clock divider by 3
Hi all,
How to Build a Clock divider by 3 with 50% duty cycle?
Input and output are listed below.
Clkin
____________
Clkout
____________
Any suggestions will be appreciated!
Best regards,
Davy
 17th October 2005, 09:59 #2
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divide by 3 clock
First you have to double input frequency, and then divide it by 3.
then divide it by 2 to produce 50% duty.
for doubling input frequency simply put one delay (such as RC, or buffer gates)
for example 20nS, then XOR input frequency and delayed one, you get 2x multiplayer.
Regards
Davood Amerion
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 17th October 2005, 09:59
 17th October 2005, 10:08 #3
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clock dividers made easy
Below is a circuit that divides incomming wave by 3 with 50% duty cycle ..
Reards,
IanP
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 17th October 2005, 10:45 #4
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clock divide by 3
I prefer Davood Amerion's method,
that would avoid clock glitching.
hi,IanP
can you assure there is no glitching in your combinational source of clock?
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 17th October 2005, 11:51 #5
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divider by 3
It looks glitchfree. It's from a Xilinx app note "Unusual Clock Dividers":
http://www.xilinx.com/xcell/xl33/xl33_30.pdf
The author repeatedly warns about possible simulator problems, but I have no problem simulating it in Verilog/ModelSim.
Both of these methods assume the input clock has 50% duty cycle, or else the output won't be symmetrical.
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 17th October 2005, 13:37 #6
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divide clock by 3
Hi Davood,
Thank you
What's "and then divide it by 3." mean?
Is it 50% duty?
Any suggestions will be appreciated!
Best regards,
Davy
 17th October 2005, 15:21 #7
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divide by 3 circuit with 50 duty cycle
The "divide it by 3" can be just an ordinary twobit counter that goes 0,1,2,0,1,2,...
After doing those steps, you would have signals like this. For the output to have 50% duty cycle, the input clock must also have 50% duty cycle.
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 17th October 2005, 17:05 #8
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divide by 3 with 50 duty cycle
Originally Posted by Davood Amerion
 17th October 2005, 17:24 #9
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clock divided by 3
Dear davyzhu,
I think the echo47's answer is complete.
Dear anjali
Because when we directly divide by 3 we can't get 50% duty (insted we get 33.3% duty)
Regards
 17th October 2005, 18:37 #10
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clock divide 3
hai davood, we can get 50% duty cycle even by directly DIVIDE BY 3. by using 2 couters (one posedge triggered & one negedge triggered) & once total count equals 3, output clk need to be toggled. i followed int his way, instead of multiplying by 2, then divide by 3, then divide by 2.
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 17th October 2005, 18:37
 18th October 2005, 02:42 #11
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divider 3
Hi echo47,
Why not go directly from "XOR" to "Divide by 6"?
Best regards,
Davy
 18th October 2005, 03:56 #12
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unusual clock dividers
oh, thanks to echo47 ,
your design is glitching free,the combinational based latch is great!
 18th October 2005, 04:35 #13
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clock dividers
You guys are giving my too much credit. ;)
I drew the timing diagram to illustrate the suggestion by Davood Amerion.
The latchbased design was suggest by IanP. The design is from "Unusual Clock Dividers" by a Xilinx applications engineer.
davyzhu, an ordinary divideby6 counter that goes 0,1,2,3,4,5,0,1,2,3,4,5,... wouldn't have 50% duty cycle. By separating the counter into divideby3 and divideby2, you get 50%. (Actually, this still is a divideby6 counter, but with a funny count sequence.)
Someone asked me which program I used to draw that timing diagram. It's just lines drawn with a CAD program. I used good old OrCAD SDT for DOS. I still use it for large project schematics. I prefer it over all the modern tools.
 18th October 2005, 06:09 #14
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esnips + clock dividers made easy
Here is one more ckt in verilog!!
Code:module clk_div3(clk,clk_out); input clk; output clk_out; reg [1:0] cnt_p, cnt_n; wire [1:0] cnt_p_nx, cnt_n_nx; initial begin cnt_p = 2'b11; cnt_n = 2'b11; end assign clk_out = cnt_p[0]  cnt_n[0]; assign cnt_p_nx = {cnt_p[0],~(cnt_p[0]  cnt_p[1])}; assign cnt_n_nx = {cnt_n[0],~(cnt_n[0]  cnt_n[1])}; always @(posedge clk) cnt_p <= cnt_p_nx; always @(negedge clk) cnt_n <= cnt_n_nx; endmodule // clk_div3
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 19th October 2005, 17:38 #15
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2/3 divider 50% duty
CLOCK DIVIDERS MADE EASY
http://www.edaboard.com/download.php?id=30847
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 20th October 2005, 03:02 #16
verilog clock divider 50 duty cycle
Thanks. it is useful for me
Originally Posted by nand_gates
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 20th October 2005, 04:43 #17
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clock divided by 3 circuit
Check this paper as well
http://www.edaboard.com/ftopic101951.html
Maybe it is the same as the one by tut.
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 30th December 2005, 09:13 #18
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xilinx application note digital clock divider
If simplicity of design strikes you, then here's a solution.
If i have a 3 bit ring counter preloaded with a value 001, then I tap the output from any point, I'd have a dividebythree 33% duty cycle output.
If i have another 3 bitring counter preloaded with same value 001, but clocked on the negative edge of the clock, I'd have another dividebythree 33% duty cycle output with phase shift of 90 degree wrt the first output.
I OR these two outputs and I get a dividebythree 50% duty cycle output. Am i right?
 31st December 2005, 10:16 #19
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clock dividers made easy.pdf
Yes that would give a 50% duty cycle (assuming the input clock is square), however I wouldn't say a sixflop solution is "simplicity of design". ;)
By the way, if those two counters should ever fall out of sync (for example by a noise glitch or cosmic ray hit), then they would stay that way forever. I recommend using selfsynchronizing logic wherever possible.
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 1st January 2006, 17:27 #20
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clk divider 3
Just so that i understand the comment. Is Davood Amerion's solution the best available? Aren't there any issues in that circuit to produce 2x frequency square waves from a XOR gate and delay elements? Isn't designing the delay element more involved than putting six standard flops? I ask this so that i get the perspective...
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