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what is the advantage of PT's timing analyasis ability?

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mhytr

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pre-layout mode in primetime

compared to Design compiler's
 

PT timing engine is much more accurate than the Design Compiler. PT is used as sign off tool, while the timing engine in DC is just to provide DC some timing sense in optimization
 

PT runs very fast compared to DC and many sign-off qualities are not present in DC timing analysis.

You can find the list of features in PT user manual which are not present in DC
 

DC working in the pre-layout period.

PT working in the post-layout period.
 

hi,
pt support more powerful analysis method,you will see same command name both in dc and pt,but,the one in pt has more option;
besides ,pt support more complex tcl script programming ,make complex timing analysis easier.

pt gui provides excellent debugging capability , much better than dc gui ---designvision ,which is so shabby.
 

DC working in the pre-layout period.

PT working in the post-layout period.
Click to expand...


PT is used to perform Pre-Layout Timing Analysis also
 

PT timinig engine is more sophoticated and robust compared to that of DC timing engine. It has lot of inbuilt capabilities with which the Full Chip STA can be done at ease. DC timing engibe is more usefull at Subblock at pre-rote stagge
 

If your design is small and simple, you can use DC.(<1M gate and <10 clock-domains)
If not, PT is the best choice.
 

we can provide timing models of our IP to the third party using PT.
 

mhytr said:
compared to Design compiler's
Click to expand...
1.As previously mentioned, the block level static timing analysis is done using DC.
2.The chip-level static timing can be performed using the STA (Primetime).
3.Primetime is the Synopsys stand-alone sign-off quality static timing analysis tool that is capable of performing extremely fast static timing analysis on full chip-level designs.
4.The static timing is performed both for the pre and post-layout gate-level net list.
5.In the pre-layout mode, Primetime uses the wire load models specified in the library to estimate the net delays.In post –layout the actual RC values can calculated
 

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