hwb
Newbie level 5
xilinx system generator digital signal processing
Hello!
After having implemented some digital audio projects in VHDL using own code or supplied IP I now want to try the System Generator for a simple upsampling from 48 to 96kHz. I am used to work with Matlab/Simulink, so it was a questions of an hour until the simulation in Simulink and ModelSim was successful. It basically consists of a gateway followed by a 1:2 interpolating FIR filter block and a gateway out per channel.
Now I have the problem to connect it to the I²S input and output streams. Has anybody successfully implemented a I²S interface in a simulink model or could provide some examples of connecting synchronous serial interfaces to a system generator design?
It seems I am having some problems to think in the continuous dataflow in simulink compared to my event and handshake-based designs in VHDL. In VHDL it was easy: If there's an event on the word-clock, the previously received audio word is stored in the corresponding register, a received flag is set, and the filter requests this sample for processing when it's ready with processing the last one. At the output, the processed data is synchronised with the audio clock again and everything is fine.
I have been trying different approaches with registers, valid inputs of the filter and others, but neither of them was working. I have no idea how to implement this in Simulink, so every help would be greatly appreciated!
Holger
Hello!
After having implemented some digital audio projects in VHDL using own code or supplied IP I now want to try the System Generator for a simple upsampling from 48 to 96kHz. I am used to work with Matlab/Simulink, so it was a questions of an hour until the simulation in Simulink and ModelSim was successful. It basically consists of a gateway followed by a 1:2 interpolating FIR filter block and a gateway out per channel.
Now I have the problem to connect it to the I²S input and output streams. Has anybody successfully implemented a I²S interface in a simulink model or could provide some examples of connecting synchronous serial interfaces to a system generator design?
It seems I am having some problems to think in the continuous dataflow in simulink compared to my event and handshake-based designs in VHDL. In VHDL it was easy: If there's an event on the word-clock, the previously received audio word is stored in the corresponding register, a received flag is set, and the filter requests this sample for processing when it's ready with processing the last one. At the output, the processed data is synchronised with the audio clock again and everything is fine.
I have been trying different approaches with registers, valid inputs of the filter and others, but neither of them was working. I have no idea how to implement this in Simulink, so every help would be greatly appreciated!
Holger
