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How to design a power on reset block and generate a delay?

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naisare

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I need to design POR block which can give immunity to glitch in the power supply.
The requirement is any power supply glitch which losts less than 1us shouldnot trigger the reset pulse. but if the glitch losts for more than 10us then rest pulse should be given..
What is the schematic for this kind of requirement.. How to avoid the big capacitor required to generate the delay..

thanx a lot
 

Re: power on reset block

You can copy circuit from original designs.
Find DS1232 in Maxim web site. Then download data sheet with DS1232 equivalent schematic.
DrWho
 

Re: power on reset block

yea.. how to generate a delay of around 5usec without using high capacitor( not more than 20pF).
I used the Inverter fallowed by Capacitor and a schmitt triger to generate the delay.. but the capacitor was very high.. Is there any other method.. or what is wrong in my simulation..
 

power on reset block

why not use a counter(50) for the delay about 100n or so?
 

Re: power on reset block

naisare,

if you understand chinese,

see here:

**broken link removed**

Added after 1 minutes:

Also ,there are some papers for por design,you can search on IEEE.
 

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