Code_Nerd
Newbie level 2
Hello, I am new to VHDL programming and am having trouble with my code for a 74LS192. The problem lies with this device having 2 clocks I think? Anyway my code is below, could you please point out any areas where I have gone wrong if possible?
Thankyou
Thankyou
Code:
library ieee;
library cypress;
use ieee.std_logic_1164.all;
use cypress.std_arith.all;
entity mod10 is
port (
cpu, cpd, clr, load : in std_logic;
tcu, tcd : buffer std_logic;
data_in : in std_logic_vector(3 downto 0);
count_value : buffer std_logic_vector(3 downto 0) );
end mod10 ;
architecture behav of mod10 is
begin
count_proc : process (cpu, cpd, clr, load)
begin
if (clr = '1') then
count_value <= "0000" ;
elsif (load = '0') then
count_value <= data_in ;
elsif (cpu'event and cpu = '1') then
if (cpd ='1' and count_value = "1001") then
count_value <= "0000" ;
elsif (cpd = '1' and count_value < "1010") then
count_value <= count_value + 1 ;
elsif (cpd'event and cpd = '1') then
if (cpu = '1' and count_value = "0000") then
count_value <= "1001" ;
elsif (cpu = '1' and count_value > "0000")then
count_value <= count_value - 1;
else count_value <= count_value ;
end if ;
end if ;
end if ;
end process count_proc;
tcu <= '0' when (count_value = "1001") else '1' ;
tcd <= '0' when (count_value = "0000") else '1' ;
end behav ;
