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manufacturers get prop delay by running transistor level spice simulations on the cell. They feed a positive and negative edge square pulse to the cell and measure the 10% - 90% point at the output of the cell. Then, they repet this process for fast/nom/worst corners. That's the number you see in manufacturer's datasheets.
Just to add one thing. Of course before manufacturing thay run several simulations, BUT... thay are all simulations after all. So what you see in the datasheet is what they eventually measure in the lab.
You can get the propagation delay by Pspice simualtion, but if you want it mathematically, here you are:
Each transistor in CMOS inverter can be represented by a resistance. This resistance depend on the mode of the MOS transsistor.
Tphl = 0.69 Req CL
Req = resistance of NMOS , CL = Load capacitance
Req = (3/4)(Vin/Idsat){1-(7/8)(lammda*Vds)}
put first Vi = Vdd then, put Vi = Vdd/2 and get Req = averege
Idsat = Kn*(W/L)*{(Vdd-Vth)Vdsat - (Vdsat^2)/2}
Propagation delay arises due to the fact that that the output of the inverter(ex:BJT) has a finite ouput capacitance.So when the output has to switch from high to low or low to high,this capacitor takes time to get charged or discharged through the collector resistor.
If you know the output capacitanc and Collector resistor value ,then propagation delay can be calculated.
See!.It is all basic network theory that is required.No software or instruments.
connect n not gates in the form of a ring where n is a odd number
now observe the waveform of one of the gates output
divide the output frequency by 2n
(this is something based on ring oscillator that i'm doing in my lab)
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