Generating constraints?

I have a few doubts on how the constraints are generated?

1)In case of constraints like slew, latency and all how can the RTL Designer generate constraints beforehand.

2)Also are there any numbers(like percentage) for giving input and output delay constraints with respect to clock.

3)How can the RTL team so precisely generate all the SDC COnstraints?

Maybe this will help you some!:|

1) In case of constraints like slew, latency and all how can the RTL Designer generate constraints beforehand.

Clock skew should be considered as a "spec" or a "constraint" that you need to meet.
So it can be decided at the very beginning of a design phase.

Although, in most cases we hope clock latency is as small as possible.
(Zero clock latency, ideally.)
But sometimes clock latency is hard to decided before the first CTS run.
---------------------------------------------------------

2) Also are there any numbers(like percentage) for giving input and output delay constraints with respect to clock.

--> For chip-level, thoes input delay and output delay should already been defined in the chip's spec. (timing diagram of the chip's spec.)

--> For block-level, proper timing budgeting is need. Maybe tools can help on this.
And it's ease for register-in register-out modules.
---------------------------------------------------------

3) How can the RTL team so precisely generate all the SDC COnstraints?

--> Designers must understand the chip spec and those RTL codes they write very well.

--> It's the designers' responsibility !

--> Right now, some tools can "aid" designers to do this.
---------------------------------------------------------