synthesis question on FSM, error on syntheis netlist!!

opt-1206

Hi,
when I synthesis a state machine, find netlist is not right (use gate simulation and formal compare check ),here is the synthsis warning, any one can tell me which warning can produce netlist error, thanks a lot

***********************************************************
Warning: ./code/statedecode.v:3792: Case branches 1 to 6 are unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3792: Case branch 8 is unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3849: Case branches 1 to 4 are unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3849: Case branches 6 to 8 are unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3792: Case branches 1 to 4 are unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3792: Case branches 6 to 8 are unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3849: Case branches 1 to 6 are unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3849: Case branch 8 is unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3849: Case branches 1 to 2 are unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3849: Case branches 4 to 8 are unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3792: Case branches 1 to 2 are unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3792: Case branches 4 to 8 are unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3849: Case branches 1 to 3 are unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3849: Case branches 5 to 8 are unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3792: Case branches 1 to 3 are unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3792: Case branches 5 to 8 are unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3849: Case branch 1 is unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3849: Case branches 3 to 8 are unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3849: Case branches 2 to 8 are unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3792: Case branch 1 is unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3792: Case branches 3 to 8 are unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3792: Case branches 2 to 8 are unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3849: Case branches 1 to 5 are unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3849: Case branches 7 to 8 are unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3792: Case branches 1 to 5 are unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3792: Case branches 7 to 8 are unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3792: Case branches 1 to 6 are unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3792: Case branch 8 is unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3849: Case branches 1 to 5 are unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3849: Case branches 7 to 8 are unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3849: Case branches 1 to 4 are unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3849: Case branches 6 to 8 are unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3792: Case branches 1 to 4 are unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3792: Case branches 6 to 8 are unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3849: Case branches 1 to 6 are unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3849: Case branch 8 is unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3849: Case branches 1 to 2 are unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3849: Case branches 4 to 8 are unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3792: Case branches 1 to 2 are unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3792: Case branches 4 to 8 are unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3849: Case branches 1 to 3 are unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3849: Case branches 5 to 8 are unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3792: Case branches 1 to 3 are unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3792: Case branches 5 to 8 are unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3849: Case branch 1 is unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3849: Case branches 3 to 8 are unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3792: Case branch 1 is unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3792: Case branches 3 to 8 are unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3849: Case branches 1 to 5 are unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3849: Case branches 7 to 8 are unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3792: Case branches 1 to 5 are unreachable. (ELAB-314)
Warning: ./code/statedecode.v:3792: Case branches 7 to 8 are unreachable. (ELAB-314)


Information: Timing loop detected. (OPT-150)
state_decode/U1971/H01 state_decode/U1971/N01 state_decode/U1970/H01 state_decode/U1970/N01 state_decode/U635/H01 state_decode/U635/N01 state_decode/performance_sync_execute_reg/H02 state_decode/performance_sync_execute_reg/N01 state_decode/U2169/H01 state_decode/U2169/N01
Information: Timing loop detected. (OPT-150)
state_decode/U2007/H01 state_decode/U2007/N01 state_decode/U2006/H01 state_decode/U2006/N01 state_decode/U1970/H03 state_decode/U1970/N01 state_decode/U635/H01 state_decode/U635/N01 state_decode/performance_sync_execute_reg/H02 state_decode/performance_sync_execute_reg/N01 state_decode/U2169/H01 state_decode/U2169/N01
Warning: Disabling timing arc between pins 'H02' and 'N01' on cell 'state_decode/performance_sync_execute_reg'
to break a timing loop. (OPT-314)
Warning: Disabling timing arc between pins 'H02' and 'N01' on cell 'state_decode/performance_execute_allowed_reg[0]'
to break a timing loop. (OPT-314)
Warning: Disabling timing arc between pins 'H02' and 'N01' on cell 'state_decode/performance_next_state_reg[4]'
to break a timing loop. (OPT-314)
Warning: Disabling timing arc between pins 'H02' and 'N01' on cell 'state_decode/performance_lic_reg'
to break a timing loop. (OPT-314)
Warning: Disabling timing arc between pins 'H02' and 'N01' on cell 'state_decode/performance_interrupt_execute_reg'
to break a timing loop. (OPT-314)
Warning: Disabling timing arc between pins 'H02' and 'N01' on cell 'state_decode/performance_next_state_reg[3]'
to break a timing loop. (OPT-314)
Warning: Disabling timing arc between pins 'H02' and 'N01' on cell 'state_decode/performance_next_state_reg[6]'
to break a timing loop. (OPT-314)
Warning: Disabling timing arc between pins 'H02' and 'N01' on cell 'state_decode/performance_next_state_reg[5]'
to break a timing loop. (OPT-314)
Warning: Disabling timing arc between pins 'H02' and 'N01' on cell 'state_decode/performance_next_state_reg[1]'
to break a timing loop. (OPT-314)
Warning: Disabling timing arc between pins 'H02' and 'N01' on cell 'state_decode/performance_next_state_reg[0]'
to break a timing loop. (OPT-314)
Warning: Disabling timing arc between pins 'H02' and 'N01' on cell 'state_decode/performance_next_state_reg[2]'
to break a timing loop. (OPT-314)

Warning: ./code/statedecode.v:3329: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3330: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3331: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3332: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3333: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3334: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3335: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3336: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3337: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3338: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3339: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3340: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3341: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3342: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3343: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3344: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3345: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3346: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3347: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3348: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3349: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3350: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3351: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3352: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3353: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3354: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3355: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3356: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3357: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3358: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3359: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3360: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3361: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3362: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3363: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3364: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3365: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3366: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3367: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3368: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3369: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3370: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3371: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3372: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3373: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3374: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3375: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3376: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3377: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3378: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3379: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3380: Intraassignment delays for nonblocking assignments are ignored. (VER-130)
Warning: ./code/statedecode.v:3381: Intraassignment delays for nonblocking assignments are ignored. (VER-130)

Information: The register 'state_decode/performance_reg_dp_input_reg[2]' is a constant and will be removed. (OPT-1206)
Information: The register 'state_decode/performance_reg_dp_input_reg[3]' is a constant and will be removed. (OPT-1206)
Information: The register 'state_decode/performance_cc_out_reg[5]' is a constant and will be removed. (OPT-1206)
Information: The register 'state_decode/performance_cc_out_reg[2]' is a constant and will be removed. (OPT-1206)
Information: The register 'state_decode/performance_cc_out_reg[0]' is a constant and will be removed. (OPT-1206)
Information: The register 'state_decode/performance_cc_out_reg[1]' is a constant and will be removed. (OPT-1206)
Information: The register 'state_decode/performance_cc_out_reg[3]' is a constant and will be removed. (OPT-1206)
Information: The register 'state_decode/performance_reg_ea_op_reg[0]' is a constant and will be removed. (OPT-1206)
Information: The register 'state_decode/performance_reg_pc_op_reg[0]' is a constant and will be removed. (OPT-1206)
********************************************************************

is a constant and will be removed.

the best way is to post ur code here... so tht people can find the error for u...

rather than posting the errors...

no offense...

regards,
sp

is a constant and will be removed. (opt-1206)

Unreachable means that no path exists from the flop o/ps to the top of the chip.
check in RTL.

Statedecode.v RTL source code.

up!

please publish your code,then you will get answer!!

statedecode.v RTL code here,thanks.

That means the FSM will not be entered.
Because your input is a constant!!!
There is no meaning to design a FSM.

This is not a FSM !
:arrow: Why there is no system clock ?
:arrow: Perhaps a simple state decoder ?

Unreachable means that the fsm your designed is constructed with error in structure. no path exists from the flop o/ps to the top of the chip.
check in RTL.

you can check your state machine code according to your state transfer diagram, then you will know which state can not be reached

The FSM contains sequential part and combinational part, but only combinational circuit description in your code.
Your code style has another issue: racing condition.
You should rewrite your FSM.

Hi,
FSM sequential part is in mainstate.v
I have modify my coding style, remove unreachable warning,but now function is still not ok.
Only one function logic is not right, Please see comments in statedecode.v "synthesis logic not right: sync". should keep sync1_state_types, but not keep now.
lots of task used in my code, somebody advise me change my task coding , what's your advise?
thanks for you reply.

up!

so many latch but not DFF generate in the netlist , why ? And I have add
//synopsys full_case parallel_case to case , also generate latch. what's the problem? thanks.

It is obvious that there are errors in your RTL codes, you should check RTL first

Hi,

I agre check your RTL code first!
I think that you must rewrite your code and before read some application notes
on FSM coding

I have remove Latch , but synthesis netlist also have logic error , I have to rewrite sync logic in another way, and now it's passed . Thanks all for your help.