Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

question of modelsim simulation ?

Status
Not open for further replies.

kimjin

Member level 3
Joined
Mar 6, 2005
Messages
61
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
1,729
i simulation the verilog code in modelsim,using the altera flex10k10 fpga,error occured during the simulation ,a internal signal goto 'Z' in sometime,and the logic become wrong,i don't know whether it's the simulator' error or my code have question,if at the clock's posedge,the sig's sample value is 'Z',will the error occur?
who have met the error,please help me?thank you.
 

Post the code dealing with the signal here.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top