wkong_zhu
Full Member level 3
I have defined a net "a" as period 12ns in UCF file, This "a" net is not a clock net direct coming from a clock PAD or DCM, but is a mux output from several clock options, such as DCM clock output; clk PAD; clock divided from DCM output, etc.
I insert a bufg before the net "a", and declare it as a TNM_NET.
Because I have active frequency switch functions in my design. I need this switch output clock. After place and route, The P&R report tell that the net has 953 fanout, and 0.52 clock skew, but the needed timing is N/A, and actual timing is also N/A. I'm quite confused about that. Why Xilinx does not recgonize this clock net.
Some help me? Thank you.
I insert a bufg before the net "a", and declare it as a TNM_NET.
Because I have active frequency switch functions in my design. I need this switch output clock. After place and route, The P&R report tell that the net has 953 fanout, and 0.52 clock skew, but the needed timing is N/A, and actual timing is also N/A. I'm quite confused about that. Why Xilinx does not recgonize this clock net.
Some help me? Thank you.
