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How to construct a JK flip-flop using transmission gates or complex gate logic?

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chihwt2003

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Hi,

Does anyone knows how to construct a JK flip-flop using Transmission gates or complex gate logic with a positive edge clock triggered?

Thanks in advance.
 

Re: JK flip-flop design

Checkout this
**broken link removed**
 

Re: JK flip-flop design

posedge triggered JK FF = -ve jk latch + +ve jk latch

latch can be designed using transmission gates easily.

for the latch design go through the book "CMOS fundamentals" (the title will be like that. i dont know the exact title, all most all people will follow that book)
 

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