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enc0unter clock tree synthesis

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jelydonut

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Im not sure if this is a problem or not.. but using the clock file below..

AutoCTSRootPin clk_pad/Y
NoGating rising
MaxDelay 3ns
MinDelay 0ns
MaxSkew 30ps
SinkMaxTran 400ps
BufMaxTran 400ps
Buffer BUX1 BUX2 BUX3 BUX4 BUX8 BUX12 BUX16 BUX20 INX1 INX2 INX3 INX4 INX8 INX12 INX16 INX20
End

it appears to synthesize and route the clock.. but during sroute i get this warning.

Reading ".sroute.def" ...
*WARNING* design has no clock net
A total of 1 warning.

Im not sure if im doing something wrong or if i can ignore the warning..

any comments is appriciated

jelydonut
 

check if the net clk_pad/Y is present in your design brower？？
 

it is.. and am i to assume that i refered to the clock pad output properly? My guess is im supposed to define the clock elsewhere earlier in the design? before sroute is performed?

jelydonut
 

You should able to do sroute before CTS or placement.

And sroute should not need the clock tree spec file.
 

Hi,
The parameters which u r described that all comes from the front end (After completion of successful synthesis then they will generate constraints file called timing constraint file[.sdc format] which consist the all parameters mentioned by u).
The "sroute" we have to do before clock tree synthesis or after the floorplan & powerplan and i think there is no relation with the CTS and the clock parameters.

"sroute" will routes the block pins, pad pins, pad rings, standard cell pins, and unconnected stripes.

hope this may help u to solve ur problem.

Prashant
 

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