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I has these IEEE papers about NOISE FOLDING and could upload them:
1. An approach to tackle quantization noise folding in double-sampling /spl Sigma//spl Delta/ modulation A/D converters
Rombouts, P.; Raman, J.; Weyten, L.;
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on [see also Circuits and Systems II: Express Briefs, IEEE Transactions on]
Volume 50, Issue 4, April 2003 Page(s):157 - 163
Digital Object Identifier 10.1109/TCSII.2003.810485
AbstractPlus | References | Full Text: PDF(428 KB) IEEE JNL
2. An efficient technique to eliminate quantisation noise folding in double-sampling /spl Sigma//spl Delta/ modulators
Rombouts, P.; Raman, J.; Weyten, L.;
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Volume 3, 26-29 May 2002 Page(s):III-707 - III-710 vol.3
Digital Object Identifier 10.1109/ISCAS.2002.1010322
AbstractPlus | Full Text: PDF(414 KB) IEEE CNF
3. A 250-kHz 94-dB double-sampling /spl Sigma//spl Delta/ modulation A/D converter with a modified noise transfer function
Rombouts, P.; De Maeyer, J.; Weyten, L.;
Solid-State Circuits, IEEE Journal of
Volume 38, Issue 10, Oct. 2003 Page(s):1657 - 1662
Digital Object Identifier 10.1109/JSSC.2003.817600
AbstractPlus | References | Full Text: PDF(406 KB) IEEE JNL
4. A 16mW, 2.23-2.45GHz fully integrated /spl Sigma//spl Delta/ PLL with novel prescaler and loop filter in 0.35/spl mu/m CMOS
Keliu Shu; Sanchez-Sinencio, E.; Silva-Martinez, J.; Embabi, S.H.K.;
Radio Frequency Integrated Circuits (RFIC) Symposium, 2003 IEEE
8-10 June 2003 Page(s):181 - 184
AbstractPlus | Full Text: PDF(309 KB) IEEE CNF
5. A new linear-time harmonic balance algorithm for cyclostationary noise analysis in RF circuits
Roychowdhury, J.S.; Feldmann, P.;
Design Automation Conference 1997. Proceedings of the ASP-DAC '97. Asia and South Pacific
28-31 Jan. 1997 Page(s):483 - 492
Digital Object Identifier 10.1109/ASPDAC.1997.600312
AbstractPlus | Full Text: PDF(760 KB) IEEE CNF
6. Design of double-sampling /spl Sigma//spl Delta/ modulation A/D converters with bilinear integrators
Rombouts, P.; De Maeyer, J.; Weyten, L.;
Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on [see also Circuits and Systems I: Regular Papers, IEEE Transactions on]
Volume 52, Issue 4, April 2005 Page(s):715 - 722
Digital Object Identifier 10.1109/TCSI.2005.844233
AbstractPlus | Full Text: PDF(576 KB) IEEE JNL
7. A low-noise folded bit-line sensing architecture for multigigabit DRAM with ultrahigh-density 6F2 cell [CMOS design]
Jong-Shik Kim; Yu-Soo Choi; Hoi-Jun Yoo; Kwang-Seok Seo;
Solid-State Circuits, IEEE Journal of
Volume 33, Issue 7, July 1998 Page(s):1096 - 1102
Digital Object Identifier 10.1109/4.701271
AbstractPlus | References | Full Text: PDF(224 KB) IEEE JNL
8. Cyclostationary noise analysis of large RF circuits with multitone excitations
Roychowdhury, J.; Long, D.; Feldmann, P.;
Solid-State Circuits, IEEE Journal of
Volume 33, Issue 3, March 1998 Page(s):324 - 336
Digital Object Identifier 10.1109/4.661198
AbstractPlus | References | Full Text: PDF(400 KB) IEEE JNL
9. Fast-switching analog PLL with finite-impulse response
Levantino, S.; Milani, M.; Samori, C.; Lacaita, A.L.;
Circuits and Systems I: Regular Papers, IEEE Transactions on [see also Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on]
Volume 51, Issue 9, Sept. 2004 Page(s):1697 - 1701
Digital Object Identifier 10.1109/TCSI.2004.834519
AbstractPlus | References | Full Text: PDF(432 KB) IEEE JNL
10. High-order single-loop double-sampling sigma-delta modulator topologies for broadband applications
Yavari, M.; Shoaei, O.;
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
23-26 May 2005 Page(s):5593 - 5596 Vol. 6
Digital Object Identifier 10.1109/ISCAS.2005.1465905
AbstractPlus | Full Text: PDF(224 KB) IEEE CNF
11. A low noise folded bit-line sensing architecture for multi-Gb DRAM with ultra high density 6F2cell
Jong-Shik Kim; Yu-Soo Choi; Hoi-Jun Yoo; Kwang-Seok Seo;
Solid-State Circuits Conference, 1997. ESSCIRC '97. Proceedings of the 23rd European
16-18 Sept. 1997 Page(s):192 - 195
AbstractPlus | Full Text: PDF(136 KB) IEEE CNF
12. An efficient decimation sinc-filter design for software radio applications
Laddomada, M.; Lo Presti, L.; Mondin, M.; Ricchiuto, C.;
Wireless Communications, 2001. (SPAWC '01). 2001 IEEE Third Workshop on Signal Processing Advances in
20-23 March 2001 Page(s):337 - 339
Digital Object Identifier 10.1109/SPAWC.2001.923919
AbstractPlus | Full Text: PDF(204 KB) IEEE CNF
13. Temporal noise in CMOS passive pixels
Fujimori, I.L.; Sodini, C.G.;
Sensors, 2002. Proceedings of IEEE
Volume 1, 12-14 June 2002 Page(s):140 - 145 vol.1
Digital Object Identifier 10.1109/ICSENS.2002.1037005
AbstractPlus | Full Text: PDF(388 KB) IEEE CNF
14. Double-Sampling Single-Loop $Sigma$$Delta$ Modulator Topologies for Broadband Applications
Yavari Mohammad ; Shoaei Omid ; Rodriguez-Vazquez Angel ;
IEEE Transactions on Circuits and Systems II: Express Briefs : Accepted for future publication
Volume PP, Issue 99, 2005 Page(s):1 - 1
Digital Object Identifier 10.1109/TCSII.2005.862036
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