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  1. #1
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    vhdl z

    In fact, I am interact with I2C bus.

    I want to get value 1 when bus is at High 'z'.

    how to implement it?

    if ( bus = 'z' )
    data <= 1;

    it can't work in synthesis.

    If use a buffer macro, Would anyone give a buffer name for any vendor product?

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    vhdl high z

    In I2C the Hi-Z state correspond to the '1' state because in the SDA line there must be a pull-up in the circuit. Check the I2C norm and you'll find it.
    So, instead of do "IF (bus ='z')" you do "IF(bus='1')".
    To test a Hi-Z state your device should measure the current that is drained in that line.


    1 members found this post helpful.

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    verilog high z

    you can use in VHDL 'h' :

    if bus='H' then
    data<='1';



    •   Alt15th September 2005, 11:59

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  4. #4
    YUV
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    vhdl pullup

    Quote Originally Posted by vitiluck
    In fact, I am interact with I2C bus.

    I want to get value 1 when bus is at High 'z'.

    how to implement it?

    if ( bus = 'z' )
    data <= 1;

    it can't work in synthesis.

    If use a buffer macro, Would anyone give a buffer name for any vendor product?
    The construction if ( bus = 'z' ) data <= 1; can't be implemented in hardvare. But I think that your main problem is in understanding of I2C bus. It doesn't require to control "z" state. Please, study I2C standard carefully.

    Regards, YUV.



    •   Alt15th September 2005, 14:52

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    vhdl z

    Thanks you all,

    I am still in confusion. Is below understanding is right?

    mycode out to either z or 0 ( two state ) which may infer to a bufifx

    standard code read the i2c bus, will get always 1 when myout is z and all other device out is z. ( i.e. with a pull up resistor, input to a standard logic z is 1 ).

    I will try in my real test.

    Is that right?

    Added after 1 minutes:

    if you set I2c bus output to 1. it should be forbidden.



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    z in vhdl

    IN FPGA io port before Read signal on SDA pin you must set port to 'H'
    SDA <= 'H'



    •   Alt16th September 2005, 07:08

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  7. #7
    YUV
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    verilog high impedance

    Quote Originally Posted by BuBEE
    IN FPGA io port before Read signal on SDA pin you must set port to 'H'
    SDA <= 'H'
    What are you talking about? We don't have to issue a high level to SDA. We even can't do that physically, because SDA is "open collector (or drain)". This pin may be only "0" or "z".
    Let's separate the problem of simulatiom from real working circuits. I have faced the same situation. As soon as SDA pin is bidirectional, we can set SDA to "1" in simulator all the time, excluding moments of reading from device (for example, acknolledge on 9th clock) and moments of writing "0" into device, of course.
    The project's code mustn't contain any analysis of levels, it must analyse transitions of SDA and SCL lines, for example START, STOP conditions, etc.
    Talking in general, it should be a state machine.
    I would like to advice you to visit http://www.opencores.org/ and find appropriate free examples there. A long ago I did that. And though I was forced to rewrite a piece of that code, I found it very useful.

    Regards, YUV.


    PS. Sorry, if I misunderstood you. I don't know VHDL. And Verilog doesn't have "H" syntax. I understood it as "1".



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    verilog compare hi-z

    Excuse me ,I wander this too !
    In fact, I am interact with I2C bus.

    I want to get value 1 when bus is at High 'z'.

    how to implement it?

    if ( bus = 'z' )
    data <= 1;

    it can't work in synthesis.

    If use a buffer macro, Would anyone give a buffer name for any vendor product?
    if (bus ='z ') // This express is not verilog !
    if (bus =='z') // however the result of ( but =='z ') will be 'X'
    if (bus ==='z ')//but case equality is not supported for synthesis
    who can solve this problem? thank you



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    verilog pullup resistor

    It is very nice of you, YUV!

    Anyone has the same question pls see explanation of YUV in this discussion.



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    verilog highz

    Hi

    why do want to detect the high impedance state ?

    Let me share my experience of this issue. It may help you.

    I have designed FPGA core for parallel port in ECP mode. A normal parallel port supports up to 200 KHz. But the same in ECP mode, it supports 25 MHz (depends on design) or more. In this protocol, i had to design the bidirectional data bus between PC parallel port and FPGA. Whenever the FPGA wants to write some data on the bus, it can write data directly. Only problem is reading the data sent by PC. This time at FPGA side, the data bus should 'Z'. First we tried to check high impedance state on bus before reading. In fact, it was not possible. Then i used to make it high impedance before reading. then it was working perfectly.


    My suggestion is it is better to make it high impedance before reading data in bidirectional signal (even in I2C) rather than checking for high impedance.


    Here i am giving simple idea about this implementation.

    Writing_Data : signal <= data;
    Reading_Data : Signal <= 'Z';
    Buffer <= signal;


    But only thing you should do is, you should make it high impedance before (atleast one clock before) you read. If you make this side (FPGA side) high impedance, then the otherside (Some other device) of the signal can be written by the data. So that you can read it.


    Regards,
    Vishwa



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    verilog bus to z

    Quote Originally Posted by Matrix_YL
    Excuse me ,I wander this too !
    In fact, I am interact with I2C bus.

    I want to get value 1 when bus is at High 'z'.

    how to implement it?

    if ( bus = 'z' )
    data <= 1;

    it can't work in synthesis.

    If use a buffer macro, Would anyone give a buffer name for any vendor product?
    if (bus ='z ') // This express is not verilog !
    if (bus =='z') // however the result of ( but =='z ') will be 'X'
    if (bus ==='z ')//but case equality is not supported for synthesis
    who can solve this problem? thank you
    For synthesis, you don't solve it with VHDL or Verilog. You solve it electrically with a pull up resistor. Effectively, a 'Z' state is logically a "disconnect" state. The pull up resistor connects the signal to '1' when all outputs (to the same signal) are in the Hi-Z or "disconnected" state.



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    vhdl high impedance

    The pull up resistor connects the signal to '1' when all outputs (to the same signal) are in the Hi-Z or "disconnected" state
    Can you say how to implement it more clearly.Best for example

    thank you



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    z vhdl

    For synthesis, the solution is circuitry. I'm going to assume you can read a circuit diagram.

    When you put the FPGA output buffer (triangle on left) into the high impedance (Z) state with sig_out <= 'Z'; the "pullup" resistor R will raise sig_out towards the Power voltage, which is interpreted as the high or '1' state. This is basic digital electronics.

    Note that it is the output circuit (buffer) that is in the hi-Z state, not the wire or signal.



  14. #14
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    pullup vhdl

    I agree with YUV.:D
    I have surprizing solution:
    when you want 'HiZ' value, set pin az input! and when you want to put output to '0',
    set pin az output and write 0 to pin.
    I mean insted of you change output pin value , simply you change direction!!!!
    Ex:
    //-------------------------
    //pin SDA
    SDAout = 0;//permanently set to zero
    SDAdir = _input;//at startup
    .....
    // 'data' must put on SDA pin
    unsignd char rb; // moving 1
    for( rb = 0x80 ; rb != 0 ; rb = rb>>1 ){
    if( data & rb )
    SDAdir = _input;//put output to 'hiz'
    else
    SDAdir = _output;//put output to '0'
    _SENDCLK;// similar to SDA pin!
    }
    SDAdir = _input;//release bus
    ....

    reards Davood Amerion



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    high z vhdl

    yes



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