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A question about Design Compiler

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mhytr

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Is the gate number of RAM/ROM included in the report of synthesis?
Or,only the area of the whole design including the RAM/ROM is reported?
 

If you include the RAM/ROM db file in synthesis. area includes RAM/ROM area.(you can get the db file from memory compiler for ur process)

you can see the area of RAM/ROM by using
report_area -hier
 

Yes. This megacell is in link library, so when reporting area, it will be included.
 

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