liu_uestc
Junior Member level 1
input signals a,b,c.d,is unrelative;output signal enosc is a register variable;
if a or b 's posedge come ,we set enosc one;if c's negedge come we set enosc
zero.else we keep enosc unchange;
who can give me the code of verilog?
here is my initial code,but it can't meet my requirement
always@(posedge a or posedge b or negedge c or negedge d)
begin
if(a==1) enosc<=1;
elseif (b==1) enosc<=1;
elseif(c==0) enosc<=1;
elseif(d==0)enosc<=0;
else enosc<=enosc;
end//because event negedge d can't change enosc sometimes;but it must change
enosc to 0,everytime ;how to change?????
if a or b 's posedge come ,we set enosc one;if c's negedge come we set enosc
zero.else we keep enosc unchange;
who can give me the code of verilog?
here is my initial code,but it can't meet my requirement
always@(posedge a or posedge b or negedge c or negedge d)
begin
if(a==1) enosc<=1;
elseif (b==1) enosc<=1;
elseif(c==0) enosc<=1;
elseif(d==0)enosc<=0;
else enosc<=enosc;
end//because event negedge d can't change enosc sometimes;but it must change
enosc to 0,everytime ;how to change?????
