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Delta-Sigma 2-2 cascade topology design technique?

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neter

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Deal all,

I will design 14bit/24MHz sampling 2-2 cascade delta-sigma ADC,Where I should to be careful design rule?stability?or power consumption?

About OTA design, How do many unity-bandwidth and settling time enough to satisfy?

Design spec:

resulation: 14bit
input bandwidth: 1MHz
Sampling speed: 24MHz
OSR=12


Thanks a lot.
 

Have you finished your design yet?
I also want to design a MASH 2-2 sigma delta ADC,but encounter some difficulties,could you give me some advice since you are experienced in this?
My design spec;
precision: 12bit
sigmal bandwhith: 2M bandpss
 

you can refer to some books
 

Hi,
you can refer to Fernando Medeiro's book - "Top-Down design of high-performance sigma-delta modulators". using it's equations may determinate the parameters of opamp and capacitive values.
 

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