Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Testbench generation for filter design

Status
Not open for further replies.
H

hwb

Newbie level 5
Joined
Aug 30, 2005
Messages
9
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,395
fir filter testbench

Hello!

I'm currently designing a simple FIR-Filter for Spartan3 with ISE and ModelSim.
The filter is connected to the outside world by a IIS Interface. Regrettably I have no Simulink available here, so simulating the design directly with supplied audio data is not possible.

Is there a way to generate a testbench out of a .wav file or at least generate sine + noise with reasonable efforts?
Any other ideas how I can verify the design with audio data?

Thank you in advance for your help!

Holger
 

Here is a way to test ur FIR filter...
1. Get VHDL or Verilog code for FIR filter ready.
2. Generate data file for (sine+ noise) using C or any other scripting file.
This you can do in C simply as follows..
for (i=0; i< MAX_DATA_POINTS; i++) {
data = sine(i) + rand();
fprintf(data_file, "%.32x\n", data);
}

You can generate sine+noise in Verilog testbench directly also
you have to write ur verilog function for sine ...
data = sine(i) + $random;
3. In ur Verilog/VHDL test bench read data value from data file and
apply it to FIR filter input each clock!


Hope this helps..
 

    H

    hwb

    Points: 2
    Helpful Answer Positive Rating
Usualy we use SystemView for filter modeling. After this we generate test vector and connect to Aldec model software
 

Hello!

Sorry for not answering for such a long time, but I've been busy with some other Projects.

Today I had the chance to try nand_gates' tip of writing the sine stimulus directly in VHDL and it works just fine.
The only problem I have is that I'm using ModelSim Starter and my design is too big for simulation without being slowed down :cry:. So routing some internal signals to pins and doing debugging with the logic analyzer is far more productive than using the simulation tool.

As I'm used to work with Matlab/Simulink I've also downloaded an evaluation version of Xilinx System Generator and try out this approach.

@soccer: I already know OpenCores.com, but I wasn't able to find a Project which helps me with my problem.

Holger
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top