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Explanation of Spartan 3 SRAM

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amirintisar

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Hello all, i am very new to FPGA desing and finding it a little difficult to understand some terminology in the Spartan 3(XC3S200) SRAM department....Mainly Block Ram and distributed.

Basically i have 16 bits of digital data coming in from an ADC and i want to store it in the (256K x 16 bit SRAM) x 2. The adc data comes in on a very slow clock (every micro second) so all i want to do is tile the data into the memory as it comes in, starting from memory adress 0. When the memory is full i want to read the data out to the computer.

I want to initialise the RAM in my verilog program, but i dont know wether to use block RAM, distributed RAM, single port or dual port. For the task at hand can anyone suggest the best strategy and explain what it means???

Thanks guys !!!!!!!!
 

spartan 3 and external ram

Welcome to the FPGA club!

You want a 1Kx18 block Select RAM. They are convenient and plentiful. You probably don't want distributed RAM for this application because it consumes regular logic fabric.

Single-port or dual-port? Well, that depends on exactly how you want to access the RAM, but dual-port is usually very helpful. You can write into one side while simultaneously reading from the other side.

If you are using ISE's XST to synthesize, then the easiest (and most portable) approach is to follow the Xilinx suggested Verilog coding style, so XST can infer the block RAM (that means it will automatically convert your Verilog register array to either single-port or dual-port block RAM). Search your ISE manual "Synthesis and Verification Design Guide" for "inferring Block SelectRAM".

Some folks prefer to explicitly instantiate RAM modules into their HDL. That works fine too, but I think it makes the HDL harder to read, and the code becomes less portable to different FPGA types.

You probably don't need to initialize the RAM. The RAM will default to all-zero initial values. Perhaps you meant "instantiate" instead.

Good luck on your project.
 

spartan 3 sram read and write

Hi, thanks for the quick reply, i had a look at the "synthesis and design verification guide"...good stuff.

What do you mean by 1K x 18 bit block RAM ?. Does this mean i am limited to 1000 18 bit values?. I am storing very high resolution CCD images which will need to use all of the 512K memory locations, so i need much more than 1000 memory locations.

If i infer the RAM, cant i then just give RAM the meory location,data and other details (cs,lb,we...) and it will store them in memory. Then all i have to do is change the memory address and data next time i am writing to it. Is that correct ?

There is also the 100Mhz SRAM Vs 50 MHz FPGA clock timing problem, which i will deal with when i understand how to write to the RAM.

Thanks !!
 

ram module verilog example spartan 3 dual port

Oops sorry! I overlooked the "K" in your message. Horrible mistake. :oops:

You need 2*256K*16 = 8 megabits. Only the monster Xilinx FPGAs contain that much memory, and you don't want to know their price. You need external RAM chips, such as the inexpensive SRAMs on the Xilinx Spartan 3 development board. You can download its schematic and docs to see how they do it.

When you infer block RAM, it is just a big HDL register array, so you write and read from it just like any other Verilog register array. If you want to operate at high speed, then pipelining issues become important. However, reading a CCD image sensor is usually comfortably slow on an FPGA.

I don't understand your concern about 100 MHz SRAM and 50 MHz clock. Are you referring to external SRAM? You are free to change the FPGA and SRAM clock rates to other convenient values. They don't mind running slower. Make them both 25 MHz if that simplifies your design. You can synthesize various clock rates by using a simple counter or a DCM.

CCD - are you doing astronomy? I'm building a hobby project FPGA interface to a 1024x1024 16-bit camera.


Here is a simple example of inferring and using a dual-port block RAM. It will go about 200 MHz in a Spartan 3.
Code: 
// Delay buffer. Xilinx ISE should infer FPGA dual-port Block RAM.
module delay_buffer (clk, idata, odata);
  parameter             desired_delay = 0;
  input                 clk;
  input          [17:0] idata;
  reg             [9:0] Waddr = desired_delay - 3;
  reg            [17:0] Wdata;
  reg            [17:0] ram [0:1023];
  reg             [9:0] Raddr = 0;
  reg            [17:0] Rdata;
  output reg     [17:0] odata;

  always @ (posedge clk) begin
    // Write data into one side of dual-port RAM
    Wdata <= idata;         // pipeline for speed
    ram[Waddr] <= Wdata;    // write to RAM
    Waddr <= Waddr + 1;     // next address
    // Read delayed data from other side of dual-port RAM
    Rdata <= ram[Raddr];    // read from RAM
    odata <= Rdata;         // pipeline for speed
    Raddr <= Raddr + 1;     // next address (or Raddr <= Waddr - desired_delay + 4)
  end
endmodule


// Demonstrate the delay buffer.
module top (clk, odata);
  input                 clk;
  reg            [17:0] idata = 10000;
  output         [17:0] odata;

  delay_buffer #(.desired_delay(15)) u1 (clk, idata, odata);

  always @ (posedge clk) begin
    idata <= idata + 1;     // generate some data
  end
endmodule
 

spartan 3 port delay

Hello, sos for the late reply, i was away. I work for a group that use CCDs for scientific applications like x-ray imaging and my project involves x - ray diffraction using CCDs. Your hobby project is probably very similar to the work i am doing. I am using the FPGAs to intercept 16 bits of data coming from a CCD (via a 200Khz ASIC). I have used various resolution CCDs, like 512 x 512, 1024 x 1024,2048 x 256. I have already made a few programs like generating histograms, filtering data to remove dark current and background noise but this SRAM is a little trickier.

Thanks for the code you gave me. All i want to do is take the 16 bits coming from the ADC(ASIC) and store them in RAM location 1, then increment the address(as you have done) then store the pixel value, and so on. Once this is all done i want to start back at memory locatoin 1, and read out all the data. What i wanted to know is how do i assign "[17:0] ram [0:1023]" to the spartan 3 address pins and data_in pins.

I usually have a seperate address ([9:0] inaddr) which i assign to the ram address pins, and another inout data ([15:0] data_inout) which i assign to the SRAM data pins.

Here is this bit of my code..I am trying to store the "adcin" data to memory address 1 and the pixel value to the memory above it.

if (record) begin
we <= 1'b0; // active 0
oe <= 1'b1; // turn ouput off
memory <= inaddr; // eg inaddr = 1
store_pixel <= 1'b1; //store the pixel number
record <= 1'b0; // turn record off

end

if (store_pixel) begin
we <= 1'b0;
oe <= 1'b1;
memory <= inaddr + 1; // inaddr = 2
store_pixel <= 1'b0;
end

assign data_inout = (record) ? adcin : 16'bz;
assign data_inout = (store_pixel) ? pixel : 16'bz;


inaddr <= inaddr + 2; // once the values have been stored i will
// increment inaddr by 2.



I hope this make some sense, i am quite new to FPGA programming so feel free to anialate my code. I have done quite a bit of reading since my last post and now realise how stupid my clock question was and also understand how much block ram the spartan3 has to offer. 12 x 16000, so i will be needing more off-board ram.Anyway, sorry for the size of this installment.

Thanks Mate !!! :D
 

spartan 3 block ram example

When you talk to an external asynchronous SRAM chip, you need to generate the address and data signals yourself. You can't reassign a Verilog register array.

You'll need to do some timing design to make sure you satisfy all the SRAM's setup and hold requirements, and to avoid data bus contention when switching between read and write.

Here is an example of very simple timing that talks to a typical external async SRAM. It inefficient, not streamlined for any particular project. It's also untested, so beware of bugs. The clock is 50 MHz. The "top" module writes eight words "wdata" to external SRAM, then reads them back into "rdata". The test bench contains an "sram" module that roughly simulates a 50ns SRAM chip. (Your SRAM manufacturer web site may have nice Verilog modules that accurately simulate your particular chip.)

Code: 
// synthesis translate_off
`timescale 1 ns / 1 ps
module test ();
  reg                   clk;
  wire                  OEn, WEn;
  wire           [14:0] ADDR;
  wire           [15:0] DATA;

  initial begin clk=0; #10 forever begin #10 clk=1; #10 clk=0; end end

  top top (.clk(clk), .OEn(OEn), .WEn(WEn), .ADDR(ADDR), .DATA(DATA));
  sram sram (.OEn(OEn), .WEn(WEn), .ADDR(ADDR), .DATA(DATA));
endmodule


module sram (OEn, WEn, ADDR, DATA);     // 32Kx16 async SRAM
  input                 OEn, WEn;
  input          [14:0] ADDR;
  inout          [15:0] DATA;
  reg            [15:0] d;
  reg                   odrive=0;
  reg            [15:0] ram [0:32767];

  assign DATA = odrive ? d : 'bz;

  always @ (posedge WEn)
    ram[ADDR] <= DATA;                  // store the data
  always @ (ADDR) begin
    d <= #10 'bx;
    d <= #50 ram[ADDR];                 // read access delay
  end
  always @ (OEn)
    odrive <= #10 ~OEn;                 // output enable delay
endmodule
// synthesis translate_on


module top (clk, OEn, WEn, ADDR, DATA);
  input                 clk;
  reg             [1:0] cycle=0;        // four clocks per RAM cycle
  reg             [9:0] count=0;        // 8 writes, then 8 reads, ...
  wire                  write, read;
  reg            [15:0] wdata;
  output reg     [14:0] ADDR;
  inout          [15:0] DATA;
  reg                   odrive=0;
  output reg            WEn=1, OEn=1;
  reg            [15:0] rdata;

  assign write = ~count[3];             // write cycle
  assign read = count[3];               // read cycle
  assign DATA = odrive ? wdata : 'bz;   // output data to RAM

  always @ (posedge clk) begin
    cycle <= cycle + 1;                 // four clocks per memory cycle
    count <= count + (cycle == 3);
    odrive<= write & (cycle != 0);      // enable the output driver
    OEn   <= ~(read & (cycle != 0));
    WEn   <= ~(write & ^cycle);         // narrow write pulse
    ADDR  <= count[2:0];
    wdata <= write ? 500+count : 'bx;   // write something
    rdata <= cycle != 0 ? rdata : ~OEn ? DATA : 'bx;
  end
endmodule
 

spartan 3 ram

Hello all,
Happy New Year!!!!!!!!!!!!!!!!!!!!
I'm facing a problem with the Digilent Spartan3 Board.I'm not able to read or write to the external SRAM.I tried the several codes my own and some sample codes from the website.But nothing came up with.
Can anyone help me to solve this problem??
 

spartan 3 external ram

Be sure you are using the correct FPGA pin numbers for the SRAM signals.
Be sure you haven't plugged anything into the A1 Expansion Connector, because it shares many SRAM signals.
 

same code for spartan 3 sram

Hiiiiiii,
Thanks for the reply.Pin connections seems to be correct as I copied it from the datasheet.
I'm using on board SRAM(ISSI 61LV25616AL).
 

spartan3 sram read

Try running the "Default Board Test Design". It includes an SRAM test mode.
**broken link removed**
 

instantiate verilog in spartan 3

thank you....I'll chk it...
 

Re: Spartan 3 RAM

I am need to interface a CCD for xray imaging with FPGA. So I require a CCD driver chip and a 12 ADC converter. After that can take the digital signals to the FPGA.
Could any one suggest me a chip which hold the driver and a 12 bit ADC in one.

I have a CCD sensor which has the following signals

P1V - Vertical shift Register (Diff)
P2V
TG - Transfer Gate
P1H - Horizontal shift Register(Diff)
P2H
SG - Summing Gate
RG - Reset Gate
OD - Output Transistor drain
RD - Reset Drain
OUT - Analog output

Do anyone know the driver for this CCD.

Thank and Regards,
Vijay
 

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