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When you are simulating your module using TestBenches, these 'M's come into picture in Process Window. They tell you the different Levels at which you can perform the simulations. These icons can be directly instantiated when the TestBench is selected in Source window.
"Simulate Behavioral VHDL Model" will just simulate the VHDL model without synthesis.
"Simulate Post-Fit VHDL Model" will do the synthesis and Fitting of CPLD. Double clicking on that Icon in "process" window 'll run synthesis as well as it 'll Fit the design and 'll generate Post-Fit simulation Model and 'll try to simulate it using ur TestBench (if everything is fine).
All just in One Double Click.
The "Simulate Post-Fit VHDL Model" 's result always right ? whether soft Simultor self will be wrong ? ModelSim shall was be trust ?
OR that 's means I can't implement my design on device if "Simulate Post-Fit VHDL Model" 's is not same as my "Simulate Behavioral VHDL Model" result , I can't implement my design on device !
Yes, if you fail the post-fit model simulation, you cannot implement your design on C/SPLDs and FPGAs.
Although we can't 100% trust EDA CAD tools, but it is very unlikely that the post-fit model doesn't correspond to the behavioural model which you have described.
Hardly anyone fails in the post-fit model sim. Most people fail the behavioural.
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