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Important design criteria for comparator used in SAR ADC

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pseudockb

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Let's say the SAR to be designed is of 8-bit, what are the important specifications for the comparator? I would like to know how to calculate how low the offset of the comparator should be, the settling time accuracy, slew rate etc. Please give me some references. Thanks
 

i think it is depend on you circuit structure
 

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To sunnyboy,
What by you mean " depend the circuit structure" ? If I use R-2R DAC , what is the difference between Capacitor type DAC or others ?
 

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Hi,
The max offset a comparator can have depends on the resolution of the ADC. If it is a 8bit ADC, then the offset should be less than 1lsb at 8bit level. A good design will be offset <1/2 lsb.
The settling time and slew rate of the comparator also depends on the conversion speed.
hope this helps.
Bakers book has some fundamentals regarding ADC design.

rgds
fred
 

is it depend on the tech you use and the resolution that the design.

regards
 

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