a question about power compiler!

now i am estimating and analyzing power of ASIC with power compiler of synopsy tools, but there are some question:

1, what is the relation of forward saif and back saif?
forward saif is generate by lib2saif, but there are sereval simulation lib and
which one should be used for generating forward saif?

i enstimate power with different back-saif which is generated by different forward saif (which generated by different simulation lib with lib2saif) , but power result is same nearly, i am puzzled, power is not relate to forward saif or just tell powe compiler the sim lib is SDPD?
i had ever combined serveral forward saif to one forward saif , but at last
power result is same too.

2. if power compiler need sdc file for report power?

one design without sdc report power 7w, but with sdc report power 800mW
however most design with sdc file power is same as report_power without sdc file i am so puzzled.

For 2nd question:
SDC should be used for synthesis. So if you just report the power after the logic/power optimization, then SDC file is necessary.
Because the synthesized netlist may have large difference from the one w/o timing constraints.
If the constraints are so loose, then maybe the netlist does not have much difference in gate count, and therefore in estimated power.
----------------------------------------------------------------------------------------------
But if you already have a netlist and want to do the power analysis by Power Compiler:
I'm not quite sure if Power Compiler will honor the set_case_analysis.
If it honor the set_case_analysis, then the estimated power consumption may have big difference. (Of course, it will look create_clock for clock definition.)