modelSim simulator's err.

n27seg
# Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity ee
# -- 
ddd 20:10:40
Compiling architecture testbench_arch of ee
# -- Compiling configuration bin27seg_cfg
# -- Loading entity ee
# -- Loading architecture testbench_arch of ee
# -- Loading entity bin27seg
# vsim -lib work -t 1ps ee 
# //  ModelSim SE 6.0 Aug 19 2004 
# //
# //  Copyright Mentor Graphics Corporation 2004
# //              All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# //  AND IS SUBJECT TO LICENSE TERMS.
# //
# Break at ee.ant line 109
# Stopped at ee.ant line 109 
[color=red]Error: can't read "FileWatch(fileName)": no such element in array[/color]

 entity ee is 
    port ( a:in std_logic;
             b:in std_logic;
             r:out std_logic);
end ee;
architecture Behavioral of  ee is
begin
           r<= a and b;
end Behavioral;

-- C:\XILINX\GATE
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Tue Aug 30 15:55:10 2005

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY ee IS
END ee;

ARCHITECTURE testbench_arch OF ee IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "c:\xilinx\gate\ee.ano";
COMPONENT gate
PORT (
a : In std_logic;
b : In std_logic;
clk : In std_logic;
q : Out INTEGER RANGE 0 TO 7;
ea : In std_logic;
y : Out std_logic
);
END COMPONENT;

SIGNAL a : std_logic;
SIGNAL b : std_logic;
SIGNAL clk : std_logic;
SIGNAL q : INTEGER RANGE 0 TO 7;
SIGNAL ea : std_logic;
SIGNAL y : std_logic;

BEGIN
UUT : gate
PORT MAP (
a => a,
b => b,
clk => clk,
q => q,
ea => ea,
y => y
);

PROCESS -- clock process for clk,
VARIABLE TX_TIME : INTEGER :=0;

PROCEDURE ANNOTATE_q(
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
STD.TEXTIO.write(TX_LOC,string'("Annotate["));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'(",q,"));
STD.TEXTIO.write(TX_LOC, q);
STD.TEXTIO.write(TX_LOC, string'("]"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
END;

PROCEDURE ANNOTATE_y(
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
STD.TEXTIO.write(TX_LOC,string'("Annotate["));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'(",y,"));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, y);
STD.TEXTIO.write(TX_LOC, string'("]"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
END;

BEGIN
CLOCK_LOOP : LOOP
clk <= transport '0';
WAIT FOR 10 ns;
TX_TIME := TX_TIME + 10;
clk <= transport '1';
WAIT FOR 10 ns;
TX_TIME := TX_TIME + 10;
ANNOTATE_q(TX_TIME);
ANNOTATE_y(TX_TIME);
WAIT FOR 40 ns;
TX_TIME := TX_TIME + 40;
clk <= transport '0';
WAIT FOR 10 ns;
TX_TIME := TX_TIME + 10;
END LOOP CLOCK_LOOP;
END PROCESS;

PROCESS -- Process for clk
VARIABLE TX_OUT : LINE;

BEGIN
-- --------------------
a <= transport '0';
b <= transport '0';
ea <= transport '0';
-- --------------------
WAIT FOR 70 ns; -- Time=70 ns
a <= transport '1';
ea <= transport '1';
-- --------------------
WAIT FOR 70 ns; -- Time=140 ns
a <= transport '0';
b <= transport '1';
-- --------------------
WAIT FOR 70 ns; -- Time=210 ns
a <= transport '1';
ea <= transport '0';
-- --------------------
WAIT FOR 70 ns; -- Time=280 ns
a <= transport '0';
b <= transport '0';
ea <= transport '0';
-- --------------------
WAIT FOR 140 ns; -- Time=420 ns
b <= transport '1';
-- --------------------
WAIT FOR 140 ns; -- Time=560 ns
a <= transport '1';
-- --------------------
WAIT FOR 70 ns; -- Time=630 ns
b <= transport '0';
-- --------------------
WAIT FOR 80 ns; -- Time=710 ns
-- --------------------

STD.TEXTIO.write(TX_OUT, string'("Total[]"));
STD.TEXTIO.writeline(results, TX_OUT);
ASSERT (FALSE) REPORT
"Success! Simulation for annotation completed" // this is the 144 line
SEVERITY FAILURE;
END PROCESS;
END testbench_arch;

CONFIGURATION gate_cfg OF ee IS
FOR testbench_arch
END FOR;
END gate_cfg;

Launching Application for process "Generate Expected Simulation Results".

Reading C:/Modeltech_6.0/tcl/vsim/pref.tcl

# 6.0

# do ee.ado
listening on address 127.0.0.1 port 1200
# ** Warning: (vlib-34) Library already exists at "work".
# resume
# Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package numeric_std
# -- Compiling entity gate
# -- Compiling architecture behavioral of gate
# Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package numeric_std
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity ee
# -- Compiling architecture testbench_arch of ee
# -- Compiling configuration gate_cfg
# -- Loading entity ee
# -- Loading architecture testbench_arch of ee
# -- Loading entity gate
# vsim -lib work -t 1ps ee
# // ModelSim SE 6.0 Aug 19 2004
# //
# // Copyright Mentor Graphics Corporation 2004
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND
# // PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# // AND IS SUBJECT TO LICENSE TERMS.
# //
# Break at ee.ant line 144
# Stopped at ee.ant line 144
Error: can't read "FileWatch(fileName)": no such element in array