A question on SNR of Delta-Sigma modulator

sigma delta snr osr

hi all,

i found it's like in all the books, theoritically the maximum SNR of DSM (say 2nd order) with sin input is calculated as:
SNR(max)=6.02N+1.76-12.9+50log(OSR), where N is the number of bit of the quantizer.

so my question is how about when the quantizer is 1-bit, or N=1, is the equation above still valid?

delta sigma adc osr snr

Yes, it's still valid. For 1 bit sigma-delta ADC, you can use OSR to impove your SNR.

-3 ,+4 delta sigma modulator

The nxing is right.

you can test it with a example.

delta sigma osr and snr

Be aware of the formula you showed there: it is just an approximation assuming the noise transfer function is a simple 2nd-order high-pass filter (i.e. H(z)=1-z^(-2)). It only gives you an upper limit estimate for quantization noise. The actual SNR depends on the loop filter you chose and also depends on your thermal noise.

single bit delta sigma modulator

thanks all.

but then my question is:
the term 6.02N is calculated based on Vref=VLSB*2^N, so for example, N=4 then VLSB=¼Vref which is true; so when N=1, VLSB should be ½Vref (is that true?)

but based on my understanding, when N=1 (1-bit), the output voltage of the quantizer is either 0 or Vref(Full scale). am i correct on this point? that means VLSB=Vref, as a result the original equation (2nd order) will be modified as:
SNR(max)=0+1.76-12.9+50log(OSR)

the simulated result is also attached comparing with the two equations:
SNR(max)=6.02*1+1.76-12.9+50log(OSR)
SNR(max)=0 +1.76-12.9+50log(OSR)

any comments are welcome
thanks!

delta sigma snr

Hi,
I am also designing a 2nd order sigma delta modulator. About your question (I’m not sure that I understand your question correctly): The output of a quantizer is either Vref or 0 but it doesn’t mean Vlsb=Vref! The output of a sigma delta is bitstream but not bits. If you used a one bit quantizaer (a comparator) then just put N=1 in the SNR(max) formula (SNR(max)=6.02*1+1.76-12.9+50log(OSR)).

Good Luck,
Tata
P.S. Please describe your problem more clearly.

snr in delta sigma

tatakt said:

Hi,
I am also designing a 2nd order sigma delta modulator. About your question (I’m not sure that I understand your question correctly): The output of a quantizer is either Vref or 0 but it doesn’t mean Vlsb=Vref! The output of a sigma delta is bitstream but not bits. If you used a one bit quantizaer (a comparator) then just put N=1 in the SNR(max) formula (SNR(max)=6.02*1+1.76-12.9+50log(OSR)).

Good Luck,
Tata
P.S. Please describe your problem more clearly.

Click to expand...

thanks Tata,

but then what is the VLSB if it's not equal to Vref? random? undefiend? what's the relationship between VLSB and Vref for 1-bit Delta Sigma Modulator?

any comments are welcome! thank you!

osr sigma delta

Hi,
In sigma delta modulators number of bits is determined by measuring SNDR. Consequentely, Vlsb is determined by: Vlsb=Vref/2^N.
Good Luck,
Tata

delta sigma osr bit

Hi.
I do agree with tatakt. In every 1-bit ADC, VLSB = Vref/2 (assuming VFS = Vref and the input range is between 0 and Vref), i.e. if the input is greater than Vref/2 then the output bit would be 1 (logicl, digital output level) and if it is less than Vref/2 then output would be 0.
However, ofcourse in some input-output characteristics we consider this comp. level as VLSB/2 (which is Vref/4 here) to make the mean of quantization error zero.
I think now it is clear that VLSB should be nothing but Vref/2. (and for an N-bit ADC, VLSB = VFS/2^N). just sketch the input-output characteristic again for yourself.

Regards,
EZT

sigma delta snr formula

ezt said:

Hi.
I do agree with tatakt. In every 1-bit ADC, VLSB = Vref/2 (assuming VFS = Vref and the input range is between 0 and Vref), i.e. if the input is greater than Vref/2 then the output bit would be 1 (logicl, digital output level) and if it is less than Vref/2 then output would be 0.
However, ofcourse in some input-output characteristics we consider this comp. level as VLSB/2 (which is Vref/4 here) to make the mean of quantization error zero.
I think now it is clear that VLSB should be nothing but Vref/2. (and for an N-bit ADC, VLSB = VFS/2^N). just sketch the input-output characteristic again for yourself.

Regards,
EZT

Click to expand...

thanks EZT, how about a simple comparator (mid-riser) as the 1-bit quantizer? in this case, the output range is [-Vref/2, Vref/2], the output step is Vref, the input threshold is at 0.

in this comparator, the input range and the quantization gain are not easily defined, then how to calculate LSB, which is the diference between input thresholds.

any comments are welcome, thank you