Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

ICT coverage: W,RNQUIE: Simulation is complete?

Status
Not open for further replies.
Q

qjlsy

Member level 3
Joined
Apr 26, 2004
Messages
63
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
653
Have anybody used Cadence's ICT platform?

When I use ICT for coverage, ncsim shows "*W,RNQUIE: Simulation is complete" at the moment it comes to run command but no simulation is run.

What does *W,RNQUIE mean? And what may be the possible reasons for it?

Thanks a lot!
 

w,rnquie

qjlsy said:
Have anybody used Cadence's ICT platform?

When I use ICT for coverage, ncsim shows "*W,RNQUIE: Simulation is complete" at the moment it comes to run command but no simulation is run.

What does *W,RNQUIE mean? And what may be the possible reasons for it?

Thanks a lot!
Click to expand...
Hi,
Try:

nchelp ncsim RNQUIE

That should give you some help on warnings/errors from NCSIM tool.

HTH
Aji
https://www.noveldv.com\
 

*w,rnquie

It sounds like you dont have any testbench. If you try to run a simulation on just RTL you will get thsi behaviour, as there is no initial block providing stimulus for a clock, reste, etc.
 

cadence ict

1). About nchlep
ncsim/RNQUIE =
Simulation is complete when there are no future events scheduled. This warning indicates that a run command has been executed and all current events have been processed.

2). Please paste your script for running ICT here. So we can know about the problem in your coverage check.
 

ncsim: *w,rnquie: simulation is complete

It could be because of the following reason:
In the run file, if you are including multiple files using concatenation character "\" followed by space, then try removing that space. Otherwise, ncverilog treats the that is the last statement in the run file and therefore the following lines will not be executed (test-bench will be the last statement and might have ignored by ncverilog because of above problem).
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top