How to know that a design has been verified completely?

• Aug 8, 2005

• #1

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dBUGGER

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verification coverage

Hi all,
Just can someone give me an idea on how to know that a design has been verified thoroughly? Suppose I do some design and then check the performance by writing a testbench with some test vectors and verifying the o/p. Now can I say that i have verified the design throughly? Else what are the steps required to ensure the same. Thank you.

Best Regards,

 

• Aug 8, 2005

• #2

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xworld2008

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verification coverage

The coverage have two .the first is code coverage, if you use some coverage tools , you should see such as:
condition coverage , code coverage , brach coverage, toggle coverage and more. when you verify , you should reach 100% of those, the tools manual will tell you which is important. Second is function coverage , this is more important than code coverage, and which coverage reach to 100% is imposible. which is coverage function of the chip you designed.

 

• Aug 8, 2005

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linuxluo

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Re: verification coverage

hi,
first measur your code coverage, after your line coverage/condition coverage/fsm converage is high enough, then measure your fucntion coverage.

 

• Aug 9, 2005

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luancao

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Re: verification coverage

There are a lot of coverage tools. Basically, three kinds of coverage, line coverage, condition coverage and branch coverage. You could never reach all of the combination of the branches.

To ensure your design is functionally right. What you should to is define what is "functionally right". Working person to person to your system guy and marketing guy to define a basic accept guideline, and then functional accept guideline. list the features from most important to least important, then test it one by one.

It depends on ... How much effort will you spend. How many man hours are available. If you test Applo to every branch and condition, maybe it will never be on the moon...

 

• Aug 9, 2005

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verification coverage

firstly code coverage must be 100%
then for function converage, but it is hard to access 100% function converage, so before you start verification, you must have a verification scheme,
normally you should verification all you main function, then run some random vector

 

• Aug 9, 2005

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verification coverage

Hi. code coverage is classical and its tools are mature. on the other hand, functional coverage is the most painful problem that EDA vendors now hope to make a breakthrough and bring some new
method to solve it. different verification eda tools target at different goals and said that their tools are better, you can refer to these tools to see their good aspect. And to keep you functional coverage high, a plenty of tanglesome work has to be done.
hope this is helpful for you.

 

• Aug 9, 2005

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verification coverage

code coverage is less important than function coverage

 

• Aug 9, 2005

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Re: verification coverage

Monitoring coverage is surely a method to see if you have reached a certain verification level. But that is not complete . There are certain conditions which you can not achieve in normal simulation environment. If you are developing an ASIC, try to do an FPGA prototyping. This will help you in running longer runs of testcases.

 

• Aug 9, 2005

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eeeraghu

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Re: verification coverage

As stated line coverage, condition coverage and branch coverage, by you all in the verification part, thanks for that, but what are the differences between these three coverages and how do the affect verification part?
This onewould be vr\ery help ful.
Thanks to all.
Raghu

 

• Aug 9, 2005

• #10

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barkha

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Re: verification coverage

difference between these coverage are -

Statement Coverage: shows how many times each statement was executed .This measure reports whether each statement is executed or not. It is also known as line coverage.

Branch Coverage: shows which case or if else branches were executed .This coverage, also called decision coverage, reports whether a test case has explored both true and false outcomes of boolean expressions in control structures.

Condition Coverage: shows how well a Boolean expression is exercised .Condition coverage measures the sub-expressions occurring in a boolean expression independently of each other and reports the true and false outcome of each of them.

Path Coverage — shows which routes through sequential branching constructs were exercised

Triggering Coverage — shows whether each process has been uniquely triggered in its sensitivity list

Toggle Coverage — shows which bits of the signals in the design have toggled

 

• Aug 10, 2005

• #11

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verification coverage

code coverage is good for your use!
but remember: u can never prove your design is comletely right!

 

• Aug 11, 2005

• #12

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soccer

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verification coverage

i remember this is a ebook of veirfication coverage which can be download in this websit. you can refer it.

 

• Aug 12, 2005

• #13

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verification coverage

I think functional coverage is the most important creatia to tell whether your design is thoroghly verified

 

• Aug 12, 2005

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amaccormack

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Re: verification coverage

All programs, includign HDL designs, have at least one redundant line and one bug. therefore by repeatedly application of this theory, you can reduce any design to one line of code which doesn't work.

 

• Aug 15, 2005

• #15

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verification coverage

first, function coverage is the most important, then , coding coverage , last , static time analysis using PrimeTime or other tools. PrimeTime need no testbentch!

 

• Aug 15, 2005

• #16

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FLEXcertifydll

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verification coverage

The prototpe need run all functional bench?

 

• Aug 15, 2005

• #17

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Re: verification coverage

I think if all functions required by the specification have

been verified, then we can say the verification process is completed.

best regards

dBUGGER said:

Hi all,
Just can someone give me an idea on how to know that a design has been verified thoroughly? Suppose I do some design and then check the performance by writing a testbench with some test vectors and verifying the o/p. Now can I say that i have verified the design throughly? Else what are the steps required to ensure the same. Thank you.

Best Regards,

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