opamp741
Full Member level 2
Hi,
I am working on a pipelined ADC and stuck with the followng problem..
I want to simulate the input sampling network (switch cap ckt) for harmonic distortion..
Basic requirement is to compare distortion for clock voltage (for switch) of 3.3V and 2.5V..
Plz give suggestion abt the simulation based on cadance and matlab..
Thanx in advance
I am working on a pipelined ADC and stuck with the followng problem..
I want to simulate the input sampling network (switch cap ckt) for harmonic distortion..
Basic requirement is to compare distortion for clock voltage (for switch) of 3.3V and 2.5V..
Plz give suggestion abt the simulation based on cadance and matlab..
Thanx in advance