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verilog-a question (about system task $fopen)

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analogman

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fopen verilog

Following is a question about Verilog-A.

I use "$fopen", input-output system task , to write simulated data to file.
And I want to write some additional data got through
some simulation to the same file.

But the file is initialized every simulation.
I don"t want to overwrite previous data.

Some programming language is easy not to overwrite the data.
(ex. With Python language, I can use "open("filename","a")")
But with Verilog-A , it's very difficult to me.

So I want some advice or suggestion.
Thank you, and sorry for my poor English.:D
 

fopen in verilog

I have not used the following thing in Verilog A but what I can suggest is to name the file with a date stamp. I suppose that there could be some system call for this....
 

verilog fopen

There is no "a" (append) option for $fopen in Verilog-A. So your problem is veru difficuit to solve in Verilog-A language. But it is strange why you need to keep all data for each simulation. Maybe you need to change your design to do the simulation at one run.
 

$fopen verilog

>Vamsi Mocherla, cooldog

Thank you very much for replying !
I am pleased to hear some suggestion.:D

I tried some ideas not to overwrite previous data in Verilog-A.
One was a Mocherla's (Thank you). Not bad.

Consequently I found it !
Not to use $fclose at last code is a answer. I can remain previous data.

I wanted to do simulation like montecarlo (ex. 800 simulation with random data),
so I had to remain data.
And now I can do it. Thank you !
 

$fopen in verilog

In the verilog 1995, there is no append mode, but in the verilog 2001, they do add some open file mode to $fopen task

you can use

t = $fopne( filename, "a" );

or

t = $fopen( filename, "a+" );
 

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