Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Setup and hold violations

Status
Not open for further replies.
S

sandysuhy

Member level 2
Joined
May 5, 2005
Messages
43
Helped
3
Reputation
6
Reaction score
2
Trophy points
1,288
Activity points
1,679
setup and hold violations

Hi,

1) If I have both setup and hold violations and only one day for submitting my design then which one should I go for and why?
2) How to avoid setup violation?
Regards
Sandeep.
 

fix hold violation

Setup violations can always be improved by cooling a chip, better regulation of its power supply or runnign at a lower clock speed. Hold violations can't be helped, so fix the holds. However, any decent set of layout tools can be set up to automatically fix these for you.

You can avoid setup violations by using a slower clock, faster cell library or process, or by trying to do less in one clock cycle: use intermediate FFs or multi-cycle paths.
 

what are the problems if you have hold violation

1. modify your code
2.modify your constraints
 

hold violations in synthesis netlist

Dear sir :
using slow corner lib to synthesis your design in order to fix setup vio.
or adjust your code .
or if you have latch or ff in your design shift it forward until you fix setup vio. (but sometimes this is done by tools )

then fix hold vio in backend because ...

people have to modify code to fixing setup vio usually when it is not easy in backend, but fix hold vio is easy at backend ..

hope it help .
 

how to fix setup and hold

bravobravo said:
Dear sir :
using slow corner lib to synthesis your design in order to fix setup vio.
or adjust your code .
or if you have latch or ff in your design shift it forward until you fix setup vio. (but sometimes this is done by tools )

then fix hold vio in backend because ...

people have to modify code to fixing setup vio usually when it is not easy in backend, but fix hold vio is easy at backend ..

hope it help .
Click to expand...

Hi. yes it is true to fix hold in BE. Can i ask why using slow corner lib to synthesis your design in order to fix setup vio?
what does it mean by "shift it forward"?
Thanks
 

how to avoid setup voilations

setup violation can be solved by descrease the clock frequency, while hold cannot
so i think you must slove hold violation first
 

how to avoid setup voilations

Fixing setup violation is the first priority. You should use device to fix it.
Hold violation is fixable even use metal.
 

setup violation means

alchip said:
Fixing setup violation is the first priority. You should use device to fix it.
Hold violation is fixable even use metal.
Click to expand...

agree with you.
 

how to fix setup violation synthesis

Sandeep,
Depends on what you mean by 'submitting your design'.
If you mean submitting your gate level netlist for backend, then fix all your setup. Backend can take care of hold easily.
If you mean submitting your layout to fab (taping out your design), then fix all your hold, since a silicon with hold violation is as good as a dead chip.
If your chip has only setup violations, you can run your chip slower and find all functional bugs, then push for bug fixes and timing fixes on your next tapeout.
If your chip has a hold time problem, then you have to respin your chip before you can do any debug.
 

how to fix setup and hold violation

In some way, setup violation can be fixed by slow down your clock, but hold time can't be fixed by this way. You should insert buffer in the path.
In prime time, use best case and min lib to check hold violation. use worst case and max lib to check setup violation
 

setup and hold worst case

if u have less timing path with hold violation , insert buffer manully .
or u can export netlist and then read it into synthesis tool , use set_min_delay to constraint the path , or do_fix_hold (a synthesis cmd )
P&R tool can fix hold vio either , but i was not familiar with.
 

fixing hold violations

good explaination by dr_dft.Fully agree with that idea.It dependes where in the design flow you are.Setup/Hold both are important for a designer.Backend designer assumes that netlist is free from the setup time violations and carry on with the flow and can fix the hold time.
If you ask in general then Fixing hold gets the priority.
 

fixing setup and hold violations

timing violation seems that somthing happens in the clock tree or your code.
Maybe you can find the problem in your synthesis process.
 

timing path setup

slow your clock frequency and fix the hold violation.
it can be done in one day.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top