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set_fix_multiple_ports_net ,what means?

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pengfan

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set_fix_multiple_ports_net ,what means?i need to know how dc works when this command is added!
 

to remove assign statements from verilog netlist
 

Just to clarify: if you have multiple ports on a module with the same net connected to them, the netlist has to insert assign statements to be able to netlist the correct functionality. However, if you use this command, it inserts buffers so that they are actually different nets, but again with the same functionality. This is required because some backend tools do not understand assign statements.
 

such as following statement in gate netlist:

assign out = in;

by running this command, DC will add a buffer to replace assign statement.

best regards




pengfan said:
set_fix_multiple_ports_net ,what means?i need to know how dc works when this command is added!
 

for adding buffer and inventer.
 

hehe,i learn some knowledge about DC,thanks alot!!
 

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