help about cwlm in back-end

after layout ,dc will re-synthesis use cwlm,while pt still use wlm from tech-library , why pt not use cwlm from dc?

Hello friend:

Let's first set this straight.

DC = RTL to Gates mapper (w optimization etc) + STA engine
PT = STA (powerful)

When you back-annotate SDF/SPEF to PT and still fail timing that means you have to re-synthesize. That is when DC comes into pic, NOT PT. You use the layout data to accurately model the net delays (WLM) and call it CWLM.

You update the old WLM from DC memory (not delete the actual lib) by:

update_lib name_of_library <CWLM file name>

Now you can use either DC STA or PT and continue the timing analysis.

In brief PT does get the updated library, otherwise what is the use of backannotated data?

Hope it helps.

hi, eda_ak & jjww110,

In fact, the wire load model or the back-annotated information are two choice in STA. In pre-layout, you don't have the back-annotated information, therefore, you have to use the wireload model ( often very inacurate ). When you have your layout you could export the back-annotated & parasitic information to your STA. That's to say, in fact, PT also use it in the post-layout STA.

About the re-syn, if you got a very "bad" library, often all the wire load is set to be simplily 0, you should follow eda_ak's words, updating the wire load model in library by what you got in the layout and re-syn. But in most cases, the wire load model provided in the worst case library are very conservative, far worse than you get in layout, in such a case, you gain little by re-syn.