cycle and event simulation

What would be the cycle simulation advantages over event? please specify?

cycle simulation is faster than event,
represents the operation of the real hardware,
is best when representing synchronous designs, complex combinational circuitry, and no signal strength resolution.
but for asynchronous even simulation is best.

regards
raghu

Faster simulation run times is the main advantage of the cycle simulation over the event simulation. But cycle simulation cannot detect glitches.

Regards
Rakesh

Hi incisive,

1. Simulation based on cycle is faster than simulation based on event.
2. It is suitable to the regression test.
3. It is suitable to the 2-value logic.

Good Luck

Cycle simulators:
Preprocess the design into a symbolic representation
— Levelized Compiled Code (LCC)
— Binary Decision Diagrams (BDD)
— Boolean and arithmetic operations
Update all circuit states simultaneously when triggered
— Using lookup tables and computational methods
— Typically on an externally defined clock edge
— The software counterpart of a hardware model

Event simulation typically traces every signal transition as it propagates through the
circuit, and continues to do so until the circuit reaches a stable state. The illustration
displays part of an event trace produced by the Verilog-XL simulator. Note that the
simulator may need to calculate the state ofa component several times during the same
simulation time instant.
Cycle simulation typically re-evaluates the state of the circuit as a whole, once upon
each external trigger, usually without evaluating any intermediate node states. Cycle
simulation can implement combinational control logic as an optimized lookup table.
Cycle simulation can map vector functions, data flow, and arithmetic calculations into
native machine instructions. For example, it may implement a multiply operation in
machine instructions, rather than as a lookup table.

you can read the book <system-on-a-chip methodology an techniques!!

for this topci, you can read some books such as "writing testbenches" Functional Verification of HDL modles.

Generally speaking, Cycle-based simulation is faster than event-driven simulation since it only executes the sampled values instead of all the occured events of signals. However this benefits will sacrify some observability of the design since some events of the signals during the clock cycle is hidden, so at first, you many simulate your design using cycle-based simulation to check whether some errors exist. If does, then the event simulation shall be followed to find out the exat errors.

During the regression phase, the cycle-based simulation is always used so as to enhance the performance of the simulator since at that time mainly the integration errors are the major causes causing the system to malfuction.

currently, the SystemVErilog provide the Clocking block to enhance such capability when constructing your testbench.