Introducing delay in signal??? need help...

hello buddies...

I have one clock signal for one circuit and I want to use same clock signal for other circuit but for other circuit clock should be slightly delayed.Let say I want to delay by 0.7 ns or 0.3 ns....how can I introduce precise delay in clock.Which components are useful for introducing delays...Please help urgently....

thnxx in advance..

joinfaisal said:

hello buddies...

I have one clock signal for one circuit and I want to use same clock signal for other circuit but for other circuit clock should be slightly delayed.Let say I want to delay by 0.7 ns or 0.3 ns....how can I introduce precise delay in clock.Which components are useful for introducing delays...Please help urgently....

thnxx in advance..

Click to expand...

is pretty fast and small delay and not so easy fix with circurit (extra AND etc. is to slow)

if symetric delay you can try using different length of trace to circurit ie 3E8 / ( 1 / 0.3E-9) = 0.09 m and FR4 board have around 4.2 in dielectric constant and give around 0.09/4.2 = 0.0214 m = 21.4 mm trace differences

my 10 cent thinking.

/Xxargs

Hi faisal,
I f you know the correct phase relationship then you can use DCM's in xilinx devices to introduce correct phase delays. That phase difference can be easily calculated once you know the operating frequency and the delay required between different clocks.

Best Regards,

How to use DCM? is the only way is to generate DCM module using the language templates and architecture wizard in xilinx and then instatiate that particular module(dcm) to the toplevel?
please look into this

hello and thnxx for reply guys..

Actualy I am not designing circuit for specific target device or so such as Xilinx etc.... I am using cadence schematic editor for desiging a circuit and I have the avaliability of traditional gates only such as inverter ,and,nor , mux, buffers etc...and I have to use these components only to produce delayed output of the input signal further more since I have to produce delay only about 0.3 or 0.7ns so the circuit should be very simple.Like I tried to use two simple inverters in series between input and output and I saw that it produces delay of about 0.4 ns so i thought that putting 2 more inverters between will produce delay of about 0.8ns but this did not happen it just increased the delay from 0.4ns to 0.55 ns and also distorted the signal little bit.So I dont understand that what will be a simple circuit to produce required amount of delay.

you can simply route the one you want to delay in a longer path.
or you design your special inverter with W/L that gives you .7 ns.

joinfaisal said:

I have one clock signal for one circuit and I want to use same clock signal for other circuit but for other circuit clock should be slightly delayed.Let say I want to delay by 0.7 ns or 0.3 ns....how can I introduce precise delay in clock.Which components are useful for introducing delays...Please help urgently....

Click to expand...

Why are you trying to introduce such a small and precise delay? You cannot control delays this precisely with components alone. If you're implementing this on an FPGA (Xilinx only supports DCMs in FPGAs), you will also need to control placement and routing. You will probably need a lot of trial-and-error attempts to get the delay you want, and it isn't guaranteed to be replicable on another board with the exact same chip model.

If the second circuit is in not in the FPGA, then you will need to look at pad delays and, as suggested by xxxargs, delays from board layout.

It's better to rethink or redo the system so that such a small delay is not needed.