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LUT(lookup table) in FPGA can be implemented in ASIC?

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look up table in asic

LUT(lookup table) in FPGA can be implemented in ASIC? Sum of Product with LUT in ASIC?
 

lookup tables in asic

LUT can not be implemented in ASIC. LUT is special in FPGA.
 

how to implement sum of product in ASIC?
 

freeinthewind said:
LUT can not be implemented in ASIC. LUT is special in FPGA.
Click to expand...

if so, how did they manage to put it inside the FPGA?
 

FPGAs are basically arrays of logic elements, where the lookup table (usually implemented in some form of EEPROM) forms part of the logic element, and this handles all combinational logic. Any combinational logic can be implemented by just simply programming this lookup EEPROM.
In ASICs, combinational logic is handled using real logic gates. So from a lookup table, you optimize it using methods like karnaugh maps and just provide the HDL code for it.
 

LUT can be implemented easily in VHDL. Just generate this table in your library and use it directly in your code. Tests show that this method uses minimum silicon area.
Best idea: change any other logic into LUT and you will see the difference.
 

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