Anybody know about wishbone?

hi everybody
anybody plz got information about wishbone interface to mii
how could i implement it on fpga
thx in advance

Can u please explain what is mii? As to my knowledge wishbone is an onchip bus, and interfacing to any other device depends on the device and as well as the onchip bus, yes u can implement whole of the devices including the bus on the FPGA depending on the number of gates usage

MII is an interface for Ethernet communication. In typical Ethernet, you have 2 sections, the MAC and the PHY. The MAC take care of all the logic (sending, receiving packets). It interface between the processor and the PHY. The PHY take care of the physical signal itself. and such things as autonegotiation. The protocol used between the MAC and PHY is usually MII (or sometime SMII).

Wishbone is a BUS architecture. In this case, it will usually be used between the processor and the MAC.

What you meen is probably a MAC with Wishbone interface (as available on opencores.org). In this case, it is well documented in the docs available on opencores. The Wishbone specs are also available there.

If you with to interface to it, you need to have a processor with Wishbone interface or a bridge from whatever bus architecture to Wishbone (ex: OPB-Wishbone, AMBA-Wishbone, ...)

see www.opencore.org, you can find some useful information.

Then MII and whisbone interface are no where related to each other they are sperated by a Mac module