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What is the re-syn in the logic design?

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ntct

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what is re-syn?

pls let me know what is re-syn in the logic design? how can i do to learn about re-syn?
thks
 

Re: what is re-syn?

I think the full term is "re-synthesizing". It means when you are not satisfied with the synthesis results, you can "re-synthesize" your design trying different attributes and implementation constraints available in synthesis tool like using available blocks, FSM encoding etc. You can also play with your design and re-synthesize it to check whether you get efficient implementation. Plz let me know if "re-syn" is something different.
 

what is re-syn?

or is it Re-synchronising??
 

what is re-syn?

i wud like to stick on with Sparc's suggestion.
Re-synthesising will b performed, when u feel ur synthesis were initially not giving good results.
at this pt, u might have to put a tighter constraints and change the options available with synthesis tools
 

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