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Twin Well CMOS Process and connection to Vdd or GNd

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Twin Well CMOS Process

Just want to confirm, the N-Well of MIMCAP and P+ poly resistor, in a p-substrate twin well process, can be connected to either Vdd or GNd. The decision as to whether to connect N-well to Vdd or GND is based on which has a cleaner signal. Is that right? Since the N-Well is simply there to shield the MIMCAP and poly resistor from the substrate.

Thanks
 

Re: Twin Well CMOS Process

From my understanding, the NW must be connected to the highest potential
just wondering how can it be tied to GND...
 

Re: Twin Well CMOS Process

Nwell is a diode connected domain to Psub. So it could be used for undershield protection. Connect to a clean reference to filer out substrate noise. That is important for high resistive or high cap areas. Make shure that your simulation contain the Nwell/Psub diode. So you can observe that the shielding reduces effectiveness at higher frequencies. Further notice that there is also inductive coupling on chip and also capacitive adjacent coupling over some tens of microns. That depends on the dBs to achieve.
 

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