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Whats the maximal process variation on a chip?

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process variation

hello, all friends:

I want to know the maximal process variation

on a chip, is it 10%? 20 %? because when

we generate clock tree, we assume that

the process variation on a chip is zero,

I think that's not a truth.

a real chip must has process variation over

it's different location, I think this will cause

clock skew.


best regards
 

process variation

you are right
clock skew has relation with process, the viariation depends on the process and your design, there are many methods to reduce the variaation, the simplest method is increase the width of metal, of there are many other method in circuit level and layout level, you can read some IEEE paper
 

Re: process variation

Clock skew would occur even if there was no process variation. If you have a buffer tree then each net of the tree will vary slightly in timing, and if you have a single clock net then it will vary and must be sliced into RC segments to be properly analysed. I think that process variation effects are negligible compared to these effects.
 

process variation

amaccormack, of course, clock skew cannot be zero completly even there are not process varation,
but i dont think you are right, process variation effects cannot be neglected especially when process scaling down to 130,90 even below
 

process variation

usually we use the worst technology library/operation condition ,i think it is also consider the process variation,is it right?
 

Re: process variation

Clock skew is always there if since the buffer and wire load is definitely different at different path to the DFF CK port. The clock tree synthesis tool is to minimize the skew by balancing the latency.

For layout tools, what you need to do is tell the layout tool which is the clock root and the CT Gen will generate the clock for you. e.g. for Astro using "create_clock" and "set_propgated_clock" in sdc file.

Don't worry about the skew if you verify the setup time by the worst case library and hold time by the best case library. The clock skew will be under control if the timing check is passed by best case/worst case check.
 

Re: process variation

These derate settings should be provied by foundry.
 

process variation

that you dont consider process variation dont mean process variation can be neglected, that is because some eda tool do it, for example placing and routing tool may use some routing algorithm that isnt sensitive with process variation. but if you want do design some high speed circuit by yourself, you must consider it
 

Re: process variation

To make on chip variation minimum, you should use both stage match and metal match. For hold time check, you can use fast data and slow clock for back-annotated SDF.
 

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