Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi..
In pipelined designs with latches we use usually use 2 phase clock system. It might happen that in clock domain the logic delay is less that Tcycle/2. So now practically that logic in the other clock domain can use some extra time to evalute the logic.
This is known as time borrowing.
You can refer to Skew Tolerant Circuit Design by David Harris for any clarifications..
it mean that in pipeline dual phase latch design , we can modify the phase relationship of first latch and the second latch to do the clock borrowing -timing borrow.
is it right?
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
