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interfacing memory with 8085 in vhdl(structural code)

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dtparekh

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interfacing memory with 8085

Respected sir,
i m trying to interface 8085 code in vhdl with memory in vhdl but we are not able to demultiplex the data bus with address bus .
address bus is ok . but data bus being bi-directional we are facing multisourcing problem.
actually is data out from two nodes ie add bus and from read but sent in the for write operation
 

data interfacing of 8085

Hi,
here is the verilog code I am using to test my 8085 verilog core!
This is in verilog you can translate this to VHDL and use it!
In case you have problem send me ur VHDL code I will correct it and
post it here!
Hope this helps you!

Code: 
module latch(/*AUTOARG*/
   // Outputs
   Q, 
   // Inputs
   D, En
   );
   input [7:0]D;
   output [7:0] Q;
   input       En;
   reg [7:0]   Q;
   
   always@(/*AS*/D or En)
     if (En) Q <= D;
endmodule // latch

module RAM(/*AUTOARG*/
   // Inouts
   DATA, 
   // Inputs
   ADDR, CS_n, RD_n, WR_n
   );
   input [15:0] ADDR;
   inout [7:0] DATA;
   input       CS_n, RD_n, WR_n;
   reg [7:0]   mem[0:(1<<16)-1];
   initial $readmemh("memory.dat",mem);
   assign      DATA = (!CS_n && !RD_n) ? mem[ADDR] : 8'bzzzzzzzz;
   always @(posedge WR_n or posedge CS_n)
     if (!WR_n && !CS_n)
       mem[ADDR] <= DATA;
endmodule // RAM

module cpu_test();
   reg                cin;                    // To cpu of cpu.v
   reg                clk;                    // To cpu of cpu.v
   reg                rst_b;                  // To cpu of cpu.v

   wire [7:0]           ad;                     // To/From cpu of cpu.v
   wire [15:0]          addr;                   // From cpu of cpu.v
   wire                 ale;                    // From cpu of cpu.v
   wire                 io_m_b;                 // From cpu of cpu.v
   wire                 rd_n;                   // From cpu of cpu.v
   wire                 s0;                     // From cpu of cpu.v
   wire                 s1;                     // From cpu of cpu.v
   wire [2:0]           src_cycle;              // From cpu of cpu.v
   wire                 wr_n;                   // From cpu of cpu.v

   cpu cpu(/*AUTOINST*/
           // Outputs
           .addr                        (addr[15:8]),
           .ale                         (ale),
           .io_m_b                      (io_m_b),
           .rd_n                        (rd_n),
           .wr_n                        (wr_n),
           .s0                          (s0),
           .s1                          (s1),
           // Inouts
           .ad                          (ad[7:0]),
           // Inputs
           .clk                         (clk),
           .rst_b                       (rst_b),
           .cin                         (cin));
   
   latch latch (
                // Outputs
                .Q                      (addr[7:0]),
                // Inputs
                .D                      (ad[7:0]),
                .En                     (ale));
   
   RAM memory(
               // Inouts
               .DATA                    (ad[7:0]),
               // Inputs
               .ADDR                    (addr[15:0]),
               .CS_n                    (io_m_b),
               .RD_n                    (rd_n),
               .WR_n                    (wr_n));
   monitor monitor();
   initial begin
      $shm_open("WAVEFORM");
      $shm_probe(cpu_test, "AS");
      clk = 1'b0;
      rst_b = 1'b0;
      #50;
      rst_b = 1'b1;
      #5000 $finish;
   end
   always #5 clk = ~clk;
   
endmodule // cpu_test
 

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