Help me design a simple Miller opamp with 200 gain

Hi,
I am a beginner to analog IC.I have read some theory but when it comes to simulation, I just get lost, even at the DC biasing stage. I am trying to design a simple (miller) opamp, which will give me a gain of like 200(either one or 2 stages), i am not worried about the freq response or comp. all I want is a diff amp with this gain a good input and output CM range . I am using cadence TSMC .25u tech. Vdd=2.5V Vss=0, two Pmos load on the top, two diff Nmos below it and nmos current mirror at the bottom. tail current 20u, so current in each arm 10u. I wanted to have like Vod=.4, I calculate all the W/l's for this much current and overdrive, but I cannot seem to control the drain voltages. how do you figure out the drain voltages? from my calculation which seem right on paper, but on cadence get one or other in linear or reverse. and I am not even sure if I have the right values of Kn,Kp and Vth's (109.7uV/AA, -25.5uV/AA, Vthp=-.53, Vth,n=.495V) what am I doing wrong? how do you ideally start the design process?? (I have attached a hand made ckt file also, Pls dont laugh at the drawing)
Can someone guide me in details as how to bias and calculate W/L, what controls the drain voltages, and stuff)? I would really appreciate it. I try each time and give up frustrated...(hope its the right place to post this) let me know if you need more info about what I tried so far, I will appreciate your help, thnx

Re: Simple Opamp.. Help

It's difficult to control the drain voltage in open loop configuration. Without negative feedback, the gain of the opamp will be so high that the transistors can be easily driven out of saturation region, making the drain voltage difficult to be controlled. You can use a common mode feedback circuit to stabilise the drain voltage. You can try connect the output of your opamp to the inverting input, making the opamp as a unity gain buffer and check the performance.

The unit for kn and kp should be A/VV instead of V/AA.

Re: Simple Opamp.. Help

but its not the gain I am worried about right now, I am trying to just bias the thing to have all of them in sat, and the output point at the middle for max swing, if you can help me figure that out... how to do the biasing and sizing correclty.. and yes, I meant uA/VV.. thnx...

Re: Simple Opamp.. Help

In your 1st stage differential amplifier, if you are using an active current mirror load then you can define the drain voltages (the Common Mode Output voltage) as Vdd - Vgsp (Vgs of the PMOS transistor).
If things don't seem to be workin gin Cadence it may be that you may be putting the input biasing wrong, or you may have the wrong parameter values for your hand calculations. YOu should try deriving the parameters from the MOS I-V curves, also you should not drive Vgs so much so that the MOS goes into the velocity saturation area. If you do want to do that then use the Id equation that takes into account the velocity saturation effect to get your hand calculation right.
If you need more clarification I will attach the circuit and explain the process again step by step.
I hope this makes it work.