How about signed adder?

adder overflow

Hi all,

I want to add two 6 bits signed digit.
Something like 6'b10_0110, the MSB '1' is negative digit,other'00100' is absolute value.
Or Something like 6'b00_0110, the MSB '0' is positive digit,other'00100' is absolute value.

How to design a signed adder to add these too signed digit?
Now I convert it to 2's complement,add, and convert it back to signed digit.
But the overflow control seems not be a easy task.
BTW, I use Verilog.

Any suggestions will be appreciated!
Best regards,
Richard

signed adder

what you are doing is in the right direction and yes overflow is sometimes tricky but you have to decide your num of valid bits by estimating the max(min) values of your results.

signed adder

hi

first u check the msb is 1 or 0 then u add with the remaining 5 bits if u get 1 then take twos complement and append 1 in the msb

16 bit signed adder

1.Use 2's complement all through the design,there is no need to convert to 1's complement.
2. If two data are both in [-1 1), and the number of bit is n, then use n+1 bit adder, there is no overflow. sum is in [-2 2),
3. n bit to n+1 bit cinversion: sign extended.
4. if you force sum into the region [-1,1), still use n+1 bit adder ,then find if MSB and the bit right to MSB(i.e. 2nd MSB) are the same(i.e. check sum[n+1] xor sum[n]) ,if same(logic result is 1'b0) ,no overflow,else if sum[n+1],sum[n] is 10, positive sum overflow occur, if sum[n+1],sum[n] is 01, negtive sum overflow(became positive).

Added after 12 minutes:

sorry, I make a mistake,
sum[n+1],sum[n] is 10 ,it meens the sum is negtive , but if you discard MSB, it becomes positive, overflow occur.
sum[n+1],sum[n] is 01 ,it meens the sum is positive, but if you discard MSB, it becomes positive, overflow occur.

overflow adder

If you want to add two 6 bits signed digit, then the results will be 7 bits. You sign extend the MSBs of the two numbers to have a result of 7 bits.
For example if you add the 6'b10_0110 (which is -26 in 2's complement) and 6'b00_0110 (which is 6), sign extended (7'b1100110 + 7'b0000110) then the result will be 7 digits (1101100) which is negative (MSB is 1) and it's -20 (if you take the 2's complement it will be 20). In that case no overflow would exist if you didn't extend the sign bits.
But in the case of adding the two 6'b100110 numbers then an overflow will occur because the result is 1001100 which is 7 bits. If you take the 6 bits only then the MSB is 0 which means positive and you have the wrong result.
If you sign extend the two bits 7'b1100110 then the result will normally be 8'b11001100 but the 8th bit can be ignored since the 7th bit is the one that shows if the number is positive or negative.
The largest negative number of 6 digits is -32. If you add it to himself it will give -64 and the 7th bit will show that is negative

how to make overflow on s4 bit adder

first check msb if its '1' then take two's complement and add the remaining bits with other number neglecting msb 's . if u get carry as '1' then take two's complement and append '1'with the msb

full signed adder

Hi davyzhu,

For my opinion, the highest bit is the control bit, the remainder bits are valued bits.

Don't think it too complex.

Good Luck