Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Can we synthesize ADC and RAM in DC?

Status
Not open for further replies.
P

power-twq

Full Member level 6
Joined
Jun 10, 2005
Messages
373
Helped
8
Reputation
16
Reaction score
3
Trophy points
1,298
Activity points
4,550
Hello, all friends:

I want to know if DC can synthesize

if we have lib for ADC and RAM.

because I feel ADC macro and RAM

macro have no difference with

MX2X1 , AND2X1 cell in standard

cell lib.

best regards
 

for ADC, if you means your synthesis is tranlate behavior RTL to netlist. i am afraid you can't. your lib may be only the GDSII lib or some abstract model. those don't not include the enough info to DC . but you can instance those modules in your design then link them in DC if you have the DC lib formats of your ADC.
for RAM. you can do the same way like ADC. otherwise, in my minds the DC will translate it to Latch or D-FF.
 

as you say
it's hard macro
DC is a compiler to compile your RTL to netlist
In my opinion
yout must set dont touch for these hard-macro
when use DC synthesis!!
 

treat as hard core,let layout deal
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top