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what is the difference of parameter and define in verilog!

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clivechen

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In verilog file, I can't make clear of the keyword parameter and define,
that is to say, in the course of synthesis, which circuit the 'parameter' create and which circuit the 'define' create?
Thanks for any advices
clivechen
 

Re: what is the difference of parameter and define in verilo

Define in verilog is used to write MACRO's whereas parameter is used where
you want to use constant or you want to make some parameter parametarizable!

`define is used for global parameterization whereas
parameter is generally used for local parameterization.

Synthesis of `define and parameter will depent on the context in which they are used!
Hope this helps you!
 

Re: what is the difference of parameter and define in verilo

a `define if a global macro. It work exactly like a #define in c/c++. `define is of global scope. If you define in a module, it still stay declared after the module.

Code: 
`define are good for setting-up constants.  Ex:

`define true 1
`define false 0

`define cycle 20 //clock period
always #(`cycle/2) clk = ~clk;

`define NAND(dval) nand #(dval)
`NAND(3) i1 (y,a,b);
`NAND(3:4:5) i2 (o,c,d);

`define debug 1
...

`ifdef debug
...
`endif

On the other hand, 'parameter' is local to a module. It is used to define a property of the module. This property can be left to default, or can be modified at instantiation of the module. For example

Code: 
module simpleadder(a,b,sum)
   parameter width = 8;

   input [width-1:0] a;
   input [width-1:0] b;
   output [width-1:0] sum;

   assign sum = a + b
endmodule

By default, the adder is 8-bit (the width parameter use the default assigned value of 8). However, the instantiator module can change parameter value.

Code: 
module top
   reg [15:0] a;
   reg [15:0] b;
   wire [15:0] sum1;
   wire [15:0] sum2;
   ...
   simpleadder add1(a,b,sum1);
   defparam add1.width = 16;
   ...
   simpleadder #(16) add2(a,b,sum2)
   ...
endmodule

Verolog 2001 also support 'localparam', which have the same scope as 'parameter', but can not be changed from outside.

Ex:

Code: 
module simpleadder(a,b,sum)
   parameter width = 8;
   localparam delay = 5;

   input [width-1:0] a;
   input [width-1:0] b;
   output [width-1:0] sum;

   assign #(delay) sum = a + b
endmodule

module top
   reg [15:0] a;
   reg [15:0] b;
   wire [15:0] sum1;
   ...
   simpleadder add1(a,b,sum1);
   defparam add1.width = 16;
   defparam add1.delay = 10; //error, delay is not accessible outside module simpleadder
   ...
endmodule
 
define is macro definitions. they make your code is easy to read. but they make no sense in code compilation ,but replacement.
 

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