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How to consider the IO pad's equivalent model including bondwire and analog pad

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trashbox

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A packaged chip need receive a high frequency(1.1GHz),sine wave,low swing(peak to peak=0.3v) signal from external. How to consider the IO pad's equivalent model including bondwire(Au wire between analog pad and pin) and analog pad in chip? My design is based on TSMC0.25 mixed signal process, what are the parameters of this IO pad's equivalent model roughly?

Or would anybody recommend any materials or papers about this issue?
Thank you very much!
 

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