PowerPCB:Error in CAM is not same as one inVerifyDesign,why?

latium design rules exist

A PCB routing has completed 100% in Blazeroutor,
then I pour the plane of the PCB in PowerPCB's Pour manager,
In Verify Design,chech connectibity got a "NO ERROR" result,

then execute File->CAM, error occors:
Clearence checking has been done for the entire design
**NO ERRORS FOUND**

Latium design rules exist,
Run Latium design verification from Tools, Verify Design...
connectivity checking has been done
Number of errors found -- 1
because there is nor position neither other detailed information,
I had to open Verify Design, which show me following information:
connectivity error :
location:
(1031.84 1296.14 L3) subnet #1 of VCCINT
explanation:
Hatch outline(1031.84 1296.14 L3)
but I use "View Report",there is no error.

I check the position carefullly, nothing wrong. I justify the via fanouting to VCCINT,in edge of the plane, the error keep exist, but the position seems floating random.

why?

There are 2 VCCINT plane,which are connected by trace of other layer. is this the reason? I can try combine them to a plane,but how to explain this phenomenon?

latium design verification

when I combine the 2 plane -- redraw them in a plane, the question is solved.

who can give me a reason? Thanks!

hatch outline error

continue ask.....