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Basic Gates In Xilinx Spartan-3...

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Hi Guys,

I like to know what are basic gates in LUT of xilinx spartan 3?

I think Xilinx use AND,OR,NOT, and XOR as a basic gate elements in their FPGA and NOR,NAND,NOR,XNOR can create from combination of those four basic elements.

BUT... I am not sure about it!

If you guys know it could you please let me know what are basic gates in xilinx FPGA?

Are they just AND,OR,NOT or it also includes XOR and more?

Also any refrence for information about this will be appreciated!

Pouya!
 

Hi Pstar,

Xilinx, and all other FPGA manu's use LUT technology, which stands for "Look Up Table". In fact, these are small ROM's. Each of these ROM's have 4 or 5 (depending on device family) inputs that are in fact the adresslines for teh ROM. Each address contains a logic value which is read out.

In practice, this means that you can make any logic function out of the inputs of the LUT and by cascading LUT's, there' virtually no end to the compelxity of functions you can build.
 

just AND OR NOT, because XOR logic can be realized by AND OR NOT.

pstar said:
Hi Guys,

I like to know what are basic gates in LUT of xilinx spartan 3?

I think Xilinx use AND,OR,NOT, and XOR as a basic gate elements in their FPGA and NOR,NAND,NOR,XNOR can create from combination of those four basic elements.

BUT... I am not sure about it!

If you guys know it could you please let me know what are basic gates in xilinx FPGA?

Are they just AND,OR,NOT or it also includes XOR and more?

Also any refrence for information about this will be appreciated!

Pouya!
Click to expand...
 

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