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Async Ram-both clock edges

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Prasanna Kumar

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How safe is it to use both clock edges to generate
write enable (gate it with the clock) to the memory. as well as read
 

If both posedge and negedge of clock can be used to generate write enable signal of RAM if you can meet timing requirements of RAM.
 

if you do carefully, it will be safe.

Prasanna Kumar said:
How safe is it to use both clock edges to generate
write enable (gate it with the clock) to the memory. as well as read
Click to expand...
 

The problem is at edge 3 where hold time on addr/data will be entirely
dependent on buffers/routing delays. Another problem is that when we use
both clock-edges, there's a restriction on the duty cycle of the clock.
These problems could be dealt with by trying to meet these by adding delay
lines/buffers - but this is not a reliable solution.
 

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