- 8th June 2005, 05:22 #1

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## barrel shifter verilog

Hi all,

How to write a barrel shifter in Verilog?

Any easy approaches will be appreciated!

Best regards,

Davy

- 8th June 2005, 05:22

- 8th June 2005, 06:35 #2

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## verilog barrel shifter

You can refer to following sample chapter from "Digital Design Principles and Practices "

by John F. Wakerly

www.ddpp.com/DDPP3_mkt/c06samp1.pdf

You try to describe it in verilog. If you face in difficulty let us know!

We will do it for you!! But its better you try first writing the code!

Hope this helps!

- 8th June 2005, 06:37 #3

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## barrel shifter vhdl

use case to synthesize a multipler. But it seems transistor array cannot be synthesized unless you use self-designed cells or plot the schematic and design it using analog method.

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- 8th June 2005, 06:37

- 8th June 2005, 15:38 #4

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## vhdl barrel shifter

You can get good example of Barrel Shifter in nnArm core code!

Hope this helps!

- 8th June 2005, 16:11 #5
## barrel shifter vhdl or verilog

hi

simple code for barrel shifter is given in VHDL primer J. Bhaskar book but it is in VHDL . I think its logic can easily be converted to Verilog code

bye

- 18th November 2006, 11:30 #6

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## barrel shifter design

////////////

module shifter_main(Q,A,C0,C1,C2,Cin,Cout);

input [7:0] A;

input C0,C1,C2,Cin;

output [7:0] Q;

output Cout;

reg [1:0]S;

always @ (C0 or C1 or C2)

if(C0) S=2'b00;

else if(C1) S=2'b01;

else if(C2) S=2'b10;

else S=2'b11;

shifter cct(Q,S,A,Cin,Cout);

end module

//////////////

module Barrel_shifter_main(A,C0,C1,C2,C3,Q);

input [7:0]A;

input C0,C1,C2,C3;

output [7:0]Q;

reg [2:0]S;

always @ (C0 or C1 or C2 or C3)

if(C0) S=3'b001;

else if(C1) S=3'b011;

else if(C2) S=3'b101;

else if(C3) S=3'b111;

else S=3'b000;

barrel_shifter shfter(A,S,Q);

end module

//

The code for the 4x1 MUX used in the Shifter;

module mux(y,d0,d1,d2,d3,s);

input d3,d2,d1,d0;

input [1:0]s;

output y;

reg y;

always @ (d0 or d1 or d2 or d3 or s)

case (s)

2'b00:y=d0;

2'b01:y=d1;

2'b10:y=d2;

2'b11:y=d3;

endcase

end module

//

module mux8x1(y,d0,d1,d2,d3,d4,d5,d6,d7,s);

input d0,d1,d2,d3,d4,d5,d6,d7;

input [2:0] s;

output y;

reg y;

always @(d0 or d1 or d2 or d3 or d4 or d5 or d6 or d7 or s)

case (s)

3'b000:y=d0;

3'b001:y=d1;

3'b010:y=d2;

3'b011:y=d3;

3'b100:y=d4;

3'b101:y=d5;

3'b110:y=d6;

3'b111:y=d7;

endcase

end module

//

module shifter(Q,S,A,Cin,Cout);

input [7:0] A;

input [1:0]S;

input Cin;

output [7:0] Q;

output Cout;

parameter d=1'b0;

reg Cout;

mux mux1(Q[7],A[7],Cin,A[6],d,S);

mux mux2(Q[6],A[6],A[7],A[5],d,S);

mux mux3(Q[5],A[5],A[6],A[4],d,S);

mux mux4(Q[4],A[4],A[5],A[3],d,S);

mux mux5(Q[3],A[3],A[4],A[2],d,S);

mux mux6(Q[2],A[2],A[3],A[1],d,S);

mux mux7(Q[1],A[1],A[2],A[0],d,S);

mux mux8(Q[0],A[0],A[1],Cin,d,S);

always @ (A or S)

case (S)

2'b00: Cout=0;

2'b01: Cout=A[0];

2'b10: Cout=A[7];

2'b11: Cout=0;

endcase

endmodule

//

//The code for the rotator;

module barrel_shifter(A,S,Q);

input [7:0]A;

input [2:0]S;

output [7:0]Q;

parameter d=1'b0;

mux8x1 mux0(Q[7],d,A[6],A[5],A[4],A[3],A[2],A[1],A[0],S);

mux8x1 mux1(Q[6],d,A[5],A[4],A[3],A[2],A[1],A[0],A[7],S);

mux8x1 mux2(Q[5],d,A[4],A[3],A[2],A[1],A[0],A[7],A[6],S);

mux8x1 mux3(Q[4],d,A[3],A[2],A[1],A[0],A[7],A[6],A[5],S);

mux8x1 mux4(Q[3],d,A[2],A[1],A[0],A[7],A[6],A[5],A[4],S);

mux8x1 mux5(Q[2],d,A[1],A[0],A[7],A[6],A[5],A[4],A[3],S);

mux8x1 mux6(Q[1],d,A[0],A[7],A[6],A[5],A[4],A[3],A[2],S);

mux8x1 mux7(Q[0],d,A[7],A[6],A[5],A[4],A[3],A[2],A[1],S);

endmodule

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- 2nd December 2006, 09:31 #7
## barrel shifter

If you are using a Xilinx chip, take a look at this application note from Xilinx :

Implementing Barrel Shifters Using Multipliers ( available @ http://direct.xilinx.com/bvdocs/appnotes/xapp195.pdf )

It explains how touse embedded multipliers to design an efficient 32 bit barrel shifter, a sample application in VHDL and verilog is available @ http://direct.xilinx.com/bvdocs/appnotes/xapp195.zip .

Hople this helped

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