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Design Compiler or Memory Compiler?

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eexuke

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Dear all,
In my design, I want to implement a single port, 11x32bit register file. I have chosen the DW IP from DC:DW_ram_r_w_s_dff, which is a Synchronous Write-Port, Asynchronous Read-Port RAM (Flip-Flop-Based). After synthesis, the gate count is about 6600xNAND2. It seems a little larger for me.So I am wondering whether memory compiler can generate a smaller regfile?
 

Hi,
1.I think registers maybe more suitable.
2. If you prefer memory. You should use rapid compiler to generate memory. Since rapid compiler use vender library to generate memory, while synopsys DW is not mapped to vendor library.
 

Design Compiler --> Synthesis Only
Memory Compiler --> Generation of hard core memoris ( black box) , for synthesis, STA
 

You have only 11x32bits, Just use flip-flops.
If you use memory, you have trouble for test.
Use flip-flops, DFT is easy. Use latches also do.
 

1.register maybe more suitable.
2. use memory ip.
 

Use memory compiler and you can get it free from foundry
 

It is a small memory, just use dc synthesis it directly.
 

yes, memory compiler can generate a small one, we use artison's memory

compiler.

eexuke said:
Dear all,
In my design, I want to implement a single port, 11x32bit register file. I have chosen the DW IP from DC:DW_ram_r_w_s_dff, which is a Synchronous Write-Port, Asynchronous Read-Port RAM (Flip-Flop-Based). After synthesis, the gate count is about 6600xNAND2. It seems a little larger for me.So I am wondering whether memory compiler can generate a smaller regfile?
 

Using memory compiler is a good choice. Virage Logic's memory compilers are the best !!!
 

Hi,
Virage Logic's memory compiler is leader in memory technology.
Use them for better.
 

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